HY27LF081G2M Hynix Semiconductor, HY27LF081G2M Datasheet
HY27LF081G2M
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HY27LF081G2M Summary of contents
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Document Title 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 1) Initial Draft. 1) Correct Fig.10 Sequential out cycle after read 2) Add the text to Fig.1, Table.1, Table.2 - text : IO15 - IO8 (x16 ...
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Revision History Revision No. 1) Correct AC characteristics(tREH) before: 30ns-> after: 20ns 2) Add Errata Case 0.5 Specification Read(all) Relaxed Except for value ID Read ID Read 1) Change AC characteristics Before 0.6 After 2) Add tADL parameter - tADL=100ns ...
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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = ...
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SUMMARY DESCRIPTION The HYNIX HY27(U/S)F(08/16)1G2M series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 1.8V Vcc Power Supply and in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the ...
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IO15 - IO8 IO7 - IO0 CLE ALE CE# RE# WE# WP# RB# Vcc Vss NC PRE Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 ...
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Figure 2. 48TSOP1 Contactions, x8 and x16 Device Figure 3. 48WSOP1 Contactions, x8 and x16 Device Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 6 ...
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Figure 4. 63FBGA Cont actions, x8 Device (Top view through package) Figure 5. 63FBGA Contactions, x16 Device (Top view through package) Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 7 ...
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PIN DESCRIPTION Pin Name DATA INPUTS/ OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable ...
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IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th Cycle A20 IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A11 4th Cycle A19 FUNCTION READ 1 READ FOR COPY-BACK READ ID RESET PAGE PROGRAM (start) COPY BACK ...
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CLE ALE CE ( NOTE: 1. With ...
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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...
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DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with four address cycles. In two consecutive read ...
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Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A18 to A27 (X8) or A17 to A26 (X16) is valid ...
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Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and 00h, ...
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Cache Read Cache read operation allows automatic download of consecutive pages the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page ...
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OTHER FEATURES 4.1 Data Protection. The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 2V(3.3V device). WP# pin pro- vides hardware ...
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Parameter Symbol Valid Block Number N VB Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient Operating Temperature (Industrial Temperature Range) T Temperature Under Bias BIAS T Storage Temperature STG (2) Input or ...
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Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 6: Block Diagram Preliminary 18 ...
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Parameter Symbol Sequential I CC1 Read Operating Current Program I CC2 Erase I CC3 Stand-by Current (TTL) I CC4 Stand-by Current (CMOS) I CC5 Input Leakage Current I LI Output Leakage Current I LO Input High Voltage V IH Input ...
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Input / Output Capacitance (1) Input Capacitance(1) Table 11: Pin Capacitance (TA= 25C, F=1.0MHz) Note: 1. For the stacked devices version the Input Capacitance is <TBD> and the I/O capacitance is <TBD> Parameter Program Time Dummy Busy ...
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Parameter CLE Setup time CLE Hold time CE# setup time CE# hold time WE# pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE# High hold time ALE to Data Loading time ...
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Pagae Block IO Program Erase 0 Pass / Fail Pass / Fail Ready/Busy Ready/Busy 6 Ready/Busy Ready/Busy 7 Write Protect Write Protect DEVI CE IDENTIFIER BYTE 1st ...
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Description 1K Page Size 2K (Without Spare Area) Reserved Reserved Spare Area Size 8 (Byte / 512Byte) 16 Standard (50ns) Serial Access Time Fast 64K Block Size 128K (Without Spare Area) 256K Reserved X8 Organization X16 Not Used Table 16: ...
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Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 7: Command Latch Cycle Figure 8: Address Latch Cycle Preliminary 24 ...
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Figure 10: Sequential Out Cycle after Read (CLE=L, WE#=H, ALE=L) Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 9. Input Data Latch Cycle Preliminary 25 ...
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Figure 12: Read1 Operation (Read One Page) Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 11: St atus Read Cycle Preliminary 26 ...
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Figure 13: Read1 Operation intercepted by CE# Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 27 ...
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Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 14 : Random Data output Preliminary 28 ...
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Figure 15: Page Program Operat ion Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 29 ...
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Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 16 : Random Data In Preliminary 30 ...
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Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 17 : Copy Back Program Preliminary 31 ...
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Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 18 : Cache Program Preliminary 32 ...
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Figure 19: Block Erase Operation (Erase One Block) Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 20: Read ID Operation Preliminary 33 ...
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Figure 21: start address at page st art :after 1st latency uninterrupted data flow Figure 22: exit from cache read in 5ms when device int ernally is reading Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit ...
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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microporcessor. The only function that was removed ...
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Figure 25: Automatic Read at Power On Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 26: Reset Operation Preliminary 36 ...
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Figure 27: Power On and Data Prot ection Timing * See the Application Not e.1 Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 37 ...
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Figure 28: Ready/Busy Pin electrical specifications Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 38 ...
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Figure 29: page programming within a block Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 39 ...
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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
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APPENDIX : Extra Features 5.1 Automatic Page0 Read after Power Up The timing diagram related to this operation is shown in Fig. 24 Due to this functionality the CPU can directly download the boot loader from the first page ...
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Figure 31. 48-pin TSOP1 20mm, Package Outline Symbol alpha Table 19: 48-TSOP1 20mm, Package Mechanical Data Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series ...
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Figure 32. 48-pin WSOP1 17mm, Package Outline Symbol alpha Table 20: 48-WSOP1 17mm, Package Mechanical Data Rev 0.7 / Apr. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series ...
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Figure 33. 63-ball FBGA - 9 ball array 0.8mm pitch, Pakage Outline NOTE: Drawing is not to scale. Symbol FD1 FE FE1 SD ...
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MARKING INFORMATION Pack ag TSOP1 SOP xFxx1G HYN NAND Flash x : Pow ...
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MARKING INFORMATION Pack ag H FBGA HY2 HY: HYN NAND Flash x: Power Supply F: Classificat ion ...
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Application Note 1. Power-on/off Sequence After power is on, the device starts an internal circuit initialization when the power supply voltage reaches a specific level. The device shows its internal initialization status with the Ready/Busy signal if initialization is on ...
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Automatic sleep mode for low power consumption The device provides the automatic sleep function for low power consumption. The device enters the automatic sleep mode by keeping CE# at VIH level for 10us without any additional command input, and ...