A43L0616B AMIC Technology, Corp., A43L0616B Datasheet - Page 15

• Manufacturer Part Number: A43L0616B
• Description: 512K x 16-Bit x 2 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

by “t
can be calculated by driving “t
then rounding up to the next higher integer. The auto refresh
command must be followed by NOP’s until the auto refresh
operation is completed. Both banks will be in the idle state at
the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us or a burst of 2048 auto refresh
cycles once in 32ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
PRELIMINARY
RC
(min)”. The minimum number of clock cycles required
(May, 2005, Version 0.0)
RC
” with clock cycle time and
14
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP’s
for a minimum time of “t
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to used
burst 2048 auto refresh cycles immediately after exiting self
refresh.
WE . Once the self refresh mode is entered, only CKE state
CS
,
RAS
RC
AMIC Technology, Corp.
” before the SDRAM reaches idle
,
CAS
and CKE with high on
A43L0616B