STPCC03 STMicroelectronics, STPCC03 Datasheet - Page 5

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STPCC03

Manufacturer Part Number
STPCC03
Description
STPC CONSUMER-S DATASHEET- PC COMPATIBLE EMBEDDED MICROPROCESSOR
Manufacturer
STMicroelectronics
Datasheet

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configured as either a two line filter with gamma
correction (primarily designed for DOS type text)
or a 3 line flicker filter (primarily designed for Win-
dows type displays). The flicker filter is optional
and can be software disabled for use with large
screen area’s of video.
The Video output pipeline of the STPC Consumer-
S interfaces directly to the internal digital TV en-
coder. It takes a 24 bit RGB non-interlaced pixel
stream and converts to a multiplexed 4:2:2 YCrCb
8 bit output stream, the logic includes a progres-
sive to interlaced scan converter and logic to in-
sert appropriate CCIR656 timing reference codes
into the output stream. It facilitates the high quality
display of VGA or full screen video streams re-
ceived via the Video input port to standard NTSC
or PAL televisions.
The digital PAL/NTSC encoder outputs interlaced
or non-interlaced video in PAL-B,D,G,H,I PAL-N,
PAL-M or NTSC-M standards and “NTSC- 4.43” is
also possible.
The four frame (for PAL) or 2 frame (for NTSC)
burst sequences are internally generated, subcar-
rier generation being performed numerically with
CKREF as reference. Rise and fall times of syn-
chronisation tips and burst envelope are internally
controlled according to the relevant ITU-R and
SMPTE recommendations.
Video output signals are directed to four analog
output pins through internal D/A converters giving,
simultaneous R,G,B and composite CVBS and S-
VHS outputs.
MEMORY CONTROLLER
The STPC handles the memory data (DATA) bus
directly, controlling from 2 to 128 MBytes. The
SDRAM controller supports accesses to the Mem-
ory Banks to/from the CPU (via the host) , from the
VIP, to/from the CRTC, to the VIDEO & to/from the
GE. (Banks 0 to 3) which can be populated with ei-
ther single or double sided 72-bit (4 bit parity)
DIMMs. Parity is not supported.
The SDRAM controller only supports 64 bit wide
Memory Banks.
Issue 1.1 - October 16, 2000
Four Memory Banks (if DIMMS are used; Single
sided or two double-sided DIMMs) are supported
in the following configurations (seeTable 1-1):
The SDRAM Controller supports buffered or un-
buffered SDRAM but not EDO or FPM modes.
SDRAMs must support Full Page Mode Type ac-
cess.
The STPC Memory Controller provides various
programmable SDRAM parameters to allow the
SDRAM interface to be optimized for different
processor bus speeds SDRAM speed grades and
CAS Latency.
IDE INTERFACE
An industry standard EIDE (ATA 2) controller is
built into the STPC Consumer-S. The IDE port is
capable of supporting a total of four devices.
POWER MANAGEMENT
The STPC Consumer-S core is compliant with the
Advanced Power Management (APM) specifica-
tion to provide a standard method by which the
BIOS can control the power used by personal
computers. The Power Management Unit module
(PMU) controls the power consumption providing
a comprehensive set of features that control the
power usage and supports compliance with the
United States Environmental Protection Agency’s
Energy Star Computer Program. The PMU pro-
vides following hardware structures to assist the
software in managing the power consumption by
the system.
- System Activity Detection.
- Three power down timers.
- Doze timer for detecting lack of system activity
for short durations.
- Stand-by timer for detecting lack of system activ-
ity for medium durations
- Suspend timer for detecting lack of system activ-
ity for long durations.
- House-keeping activity detection.
- House-keeping timer to cope with short bursts of
house-keeping activity while dozing or in stand-by
Table 1-1. Supported Memory Configs
Memory
1Mx64
2Mx64
4Mx64
Bank
size
Number
16
4
8
GENERAL DESCRIPTION
Organisation
1Mx16
2Mx8
4Mx4
Device
16Mbit
size
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