STPCC03 STMicroelectronics, STPCC03 Datasheet - Page 10

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STPCC03

Manufacturer Part Number
STPCC03
Description
STPC CONSUMER-S DATASHEET- PC COMPATIBLE EMBEDDED MICROPROCESSOR
Manufacturer
STMicroelectronics
Datasheet

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PIN DESCRIPTION
Table 2-2. Definition of Signal Pins
10/59
BASIC CLOCKS AND RESETS
SYSRSTI#
SYSRSTO#
XTALI
XTALO
HCLK
DEV_CLK
DCLK
V
MEMORY INTERFACE
MCLKI
MCLKO
CS#[3:0]
BA[0]
MA[10:0]
MD[63:0]
RAS#[1:0]
CAS#[1:0]
MWE#
DQM[7:0]
PCI INTERFACE
PCI_CLKI
PCI_CLKO
AD[31:0]
CBE#[3:0]
FRAME#
IRDY#
TRDY#
LOCK#
DEVSEL#
STOP#
PAR
SERR#
PCI_REQ#[2:0]
PCI_GNT#[2:0]
PCI_INT[3:0]
VDD5
ISA CONTROL
ISA_CLK
ISA_CLK2X
OSC14M
LA[23:17]
Note
Note
Note
DD
_xxx_PLL
2
1
2
3
; These pins must be connected to the 2.5Vpower supply. They must not be connected to the 3.45V supply.
; Denotes that the pin is V
2
; see Table 2-5 for the detail of individual V
2
2
2
2
2
2
2
2
2
2
2
2
Signal Name
2
2
2
2
2
2
2
1
2
2
5T
(see Section 4 )
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Issue 1.1 - October 16, 2000
System Power Good Input
System Reset Output
14.3MHz Crystal Input
14.3MHz Crystal Output - External Oscillator Input
Host Clock (Test)
24MHz Peripheral Clock (floppy drive)
27-135MHz Graphics Dot Clock
Power Supply for PLL Clocks
Memory Clock Input
Memory Clock Output
Memory Bank Chip Select
Memory Row & Column Address/Bank Address
Memory Row & Column Address
Memory Data
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
33MHz PCI Input Clock
33MHz PCI Output Clock (from internal PLL)
PCI Address / Data
Bus Commands / Byte Enables
Cycle Frame
Initiator Ready
Target Ready
PCI Lock
Device Select
Stop Transaction
Parity Signal Transactions
System Error
PCI Request
PCI Grant
PCI Interrupt Request
5V Power Supply for PCI ESD protection
ISA Clock Output - Multiplexer Select Line For IPC
ISA Clock x2 Output - Multiplexer Select Line For IPC
ISA bus synchronisation clock
Unlatched Address
5T
signals
Description
Qty
11
64
32
1
1
1
1
1
1
1
1
1
4
1
2
2
1
8
1
1
4
1
1
1
1
1
1
1
1
3
3
4
4
1
1
1
7

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