STPCC03 STMicroelectronics, STPCC03 Datasheet - Page 17

• Manufacturer Part Number: STPCC03
• Description: STPC CONSUMER-S DATASHEET- PC COMPATIBLE EMBEDDED MICROPROCESSOR
• Manufacturer: STMicroelectronics

PDRQ Primary DMA Request.
SDRQ Secondary DMA Request.
DMA request from IDE channels.
PDACK# Primary DMA Acknowledge.
SDACK# Secondary DMA Acknowledge.
DMA acknowledge to IDE channels.
PDIOR#, PDIOW# Primary I/O Read & Write.
SDIOR#, SDIOW# Secondary I/O Read & Write .
Primary & Secondary channel read & write.
2.2.8 Monitor Interface
RED, GREEN, BLUE RGB Video Outputs. These
are the 3 analog color outputs from the RAM-
DACs. These signals are sensitive to interference,
therefore they need to be properly shielded.
VSYNC Vertical Synchronisation Pulse. This is
the vertical synchronization signal from the VGA
controller.
HSYNC Horizontal Synchronisation Pulse. This is
the horizontal synchronization signal from the
VGA controller.
VREF_DAC DAC Voltage reference. An external
voltage reference is connected to this pin to bias
the DAC.
RSET Resistor Current Set. This reference cur-
rent input to the RAMDAC is used to set the full-
scale output of the RAMDAC.
COMP Compensation. This is the RAMDAC com-
pensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
V
2.2.9 VIDEO INPUT
VCLK Pixel Clock Input. This signal is used to syn-
chronise data being transfered from an external
video device to either the frame buffer, or alterna-
tively out the TV output in bypass mode. This pin
can be sourced from STPC if no external VCLK is
detected, or can be input from an external video
clock source.
VIN[7:0] YUV Video Data Input CCIR 601 or 656.
Time multiplexed 4:2:2 luminance and chromi-
nance data as defined in ITU-R Rec601-2 and
Rec656 (except for TTL input levels). This bus
typically carries a stream of Cb,Y,Cr,Y digital vid-
eo at VCLK frequency, clocked on the rising edge
(by default) of VCLK.
DD
to damp oscillations.
Issue 1.1 - October 16, 2000
2.2.10 TV OUTPUT
RED_TV / C_TV Analog video outputs synchro-
nized with CVBS. This output is current-driven and
must be connected to analog ground over a load
resistor (R
simple analog low pass filter is recommended. In
S-VHS mode, this is the Chrominance Output.
GREEN_TV / Y_TV Analog video outputs syn-
chronized with CVBS. This output is current-driv-
en and must be connected to analog ground over
a load resistor (R
tor, a simple analog low pass filter is recommend-
ed. In S-VHS mode, this is the Luminance Output.
BLUE_TV / CVBS Analog video outputs synchro-
nized with CVBS. This output is current-driven and
must be connected to analog ground over a load
resistor (R
simple analog low pass filter is recommended. In
S-VHS mode, this is a second composite output.
CVBS Analog video composite output (luminance/
chrominance). CVBS is current-driven and must
be connected to analog ground over a load resis-
tor (R
analog low pass filter is recommended.
IREF1_TV Ref. current for CVBS 10-bit DAC.
IREF2_TV Reference current for RGB 9-bit DAC.
VREF1_TV Ref. voltage for CVBS 10-bit DAC.
VREF2_TV Reference voltage for RGB 9-bit DAC.
VSSA_TV Analog V
VDDA_TV Analog V
VCS Line synchronisation Output. This pin is an
input in ODDEV+HSYNC or VSYNC + HSYNC or
VSYNC slave modes and an output in all other
modes (master/slave)
ODD_EVEN Frame Synchronisation Ourput. This
pin supports the Frame synchronisation signal. It
is an input in slave modes, except when sync is
extracted from YCrCbdata, and an output in mas-
ter mode and when sync is extracted from YCrCb
data
The signal is synchronous to rising edge of DCLK.
The default polarity for this pin is:
- odd (not-top) field : LOW level
- even (bottom) field : HIGH level
LOAD
). Following the load resistor, a simple
LOAD
LOAD
). Following the load resistor, a
). Following the load resistor, a
LOAD
SS
DD
). Following the load resis-
for DACs.
for DACs.
PIN DESCRIPTION
17/59