M50FLW080A STMicroelectronics, M50FLW080A Datasheet - Page 17

• Manufacturer Part Number: M50FLW080A
• Description: 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: STMicroelectronics

Table 9. LPC Bus Write Field Definitions (1 Byte)
Figure 10. LPC Bus Write Waveforms (1 Byte)
Table 10. A/A Mux Bus Operations
Number
Bus Read
Bus Write
Output Disable
Reset
Clock
Cycle
11-12
3-10
13
14
15
16
17
1
2
Operation
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
Count
Clock
Cycle
1
1
8
2
1
1
1
1
1
CYCTY
START
ADDR
SYNC
Field
DATA
PE +
TAR
TAR
TAR
TAR
DIR
V
IL
V
V
V
or V
G
IH
IH
IL
START
LAD0-
011Xb
0000b
1111b
1111b
0000b
1111b
1111b
LAD3
XXXX
XXXX
(float)
(float)
IH
1
CYCTYPE
V
IL
+ DIR
Memory
V
V
1
V
W
or V
IH
IH
IL
N/A
I/O
O
O
O
I
I
I
I
I
IH
ADDR
8
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
indicates the direction of transfer: 1b for write. Bit 0 is don’t
care (X).
A 32-bit address is transferred, with the most significant
nibble first. A23-A31 must be set to 1. A22=1 for memory
access, and A22=0 for register access.
appropriate values for A21-A20.
Data transfer is two cycles, starting with the least significant
nibble.
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
The LPC Flash Memory takes control of LAD0-LAD3 during
this cycle.
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating it has received data or a command.
The LPC Flash Memory drives LAD0-LAD3 to 1111b,
indicating a turnaround cycle.
The LPC Flash Memory floats its outputs and the host takes
control of LAD0-LAD3.
V
V
V
RP
V
IH
IH
IH
IL
DATA
2
TAR
V
2
Don't Care
Don't Care
Don't Care
CC
M50FLW080A, M50FLW080B
Description
V
or V
PP
PPH
SYNC
1
Table 5.
TAR
2
Data Output
Data Input
DQ7-DQ0
AI04430
Hi-Z
Hi-Z
shows the
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