M50FLW080A STMicroelectronics, M50FLW080A Datasheet
M50FLW080A
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M50FLW080A Summary of contents
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... PLCC32 (K) TSOP32 (NB 14mm TSOP40 ( 20mm PROGRAM/ERASE SUSPEND – Read other Blocks/Sectors during Program Suspend – Program other Blocks/Sectors during Erase Suspend ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code (M50FLW080A): 80h – Device Code (M50FLW080B): 81h PRODUCT PREVIEW 1/53 ...
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... Table 1. Signal Names (FWH/LPC Interface Table 2. Signal Names (A/A Mux Interface Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Addresses (M50FLW080A Table 4. Addresses (M50FLW080B SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 10 Input/Output Communications (FWH0/LAD0-FWH3/LAD3 Input Communication Frame (FWH4/LFRAME Identification Inputs (ID0-ID3) ...
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... Program/Erase Controller Status (Bit SR7 Erase Suspend Status (Bit SR6 Erase Status (Bit SR5 Program Status (Bit SR4 Status (Bit SR3 Program Suspend Status (Bit SR2 Block/Sector Protection Status (Bit SR1 Reserved (Bit SR0 Table 14. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 M50FLW080A, M50FLW080B 3/53 ...
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... M50FLW080A, M50FLW080B FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS . . . 24 Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 15. Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 16. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 17. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register . . . . . . . . . . . . . . 25 Manufacturer Code Register ...
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... PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 33. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 34. M50FLW080A Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . . 41 Table 35. M50FLW080B Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . . 43 APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only Figure 24 ...
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... M50FLW080A, M50FLW080B SUMMARY DESCRIPTION The M50FLW080 Mbit (1M x8) non-volatile memory that can be read, erased and repro- grammed. These operations can be performed us- ing a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing on production lines, an optional 12V power supply can be used to reduce the erasing and programming time ...
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... AI09230B M50FLW080A, M50FLW080B Input/Output Communications Input Communication Frame Identification Inputs (ID0 and ID1 are Reserved for Future Use (RFU) in LPC mode) General Purpose Inputs Interface Configuration Interface Reset CPU Reset Clock Top Block Lock Write Protect Reserved for Future Use ...
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... M50FLW080A, M50FLW080B Figure 4. PLCC Connections A/A Mux DQ0 FWH0/LAD0 A/A Mux Note: Pins 27 and 28 are not internally connected. Figure 5. TSOP32 Connections A10 8/ GPI1 GPI0 WP TBL M50FLW080A ID3 9 M50FLW080B ID2 ...
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... Figure 6. TSOP40 Connections A10 Table 3. Addresses (M50FLW080A) Block Size Address Range (KByte) 64 F0000h-FFFFFh 64 E0000h-EFFFFh 64 D0000h-DFFFFh 64 C0000h-CFFFFh 64 B0000h-BFFFFh 64 A0000h-AFFFFh 64 90000h-9FFFFh 64 80000h-8FFFFh 64 70000h-7FFFFh 64 60000h-6FFFFh 64 50000h-5FFFFh 64 40000h-4FFFFh 64 30000h-3FFFFh 64 20000h-2FFFFh 64 10000h-1FFFFh 64 00000h-0FFFFh Note: Also see APPENDIX A ...
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... M50FLW080A, M50FLW080B SIGNAL DESCRIPTIONS There are two distinct bus interfaces available on this device. The active interface is selected before power-up, or during Reset, using the Interface Configuration Pin, IC. The signals for each interface are discussed in the Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions ...
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... V should not be set hours during the life of the memory. V Ground age measurements. M50FLW080A, M50FLW080B Supply Voltage CC becomes valid, the Command Interface is Supply Voltage pins and the V Supply Voltage pins must program and erase operations ...
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... M50FLW080A, M50FLW080B Table 5. Memory Identification Input Configuration (LPC mode) Memory Number 1 (Boot memory BUS OPERATIONS The two interfaces, A/A Mux and FWH/LPC, sup- port similar operations, but with different bus sig- nals and timings. The Firmware Hub/Low Pin Count (FWH/LPC) Interface offers full functional- ...
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... Reset mode when RP is Low held Low, V during a Program or Erase operation, the opera- tion is aborted, and the affected memory cells no longer contain valid data. The memory can take PLRH M50FLW080A, M50FLW080B , and Output IH . The Data Inputs/Outputs will IL Figure 17., and Table ...
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... M50FLW080A, M50FLW080B Table 6. FWH Bus Read Field Definitions Clock Clock FWH0- Cycle Cycle Field FWH3 Number Count 1 1 START 1101b 2 1 IDSEL XXXX 3-9 7 ADDR XXXX 10 1 MSIZE XXXX 11 1 TAR 1111b 1111b 12 1 TAR (float) 13-14 2 WSYNC 0101b 15 1 RSYNC 0000b 16-17 M=2n DATA ...
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... The FWH Flash Memory drives FWH0-FWH3 to 1111b, 1111b O indicating a turnaround cycle. 1111b The FWH Flash Memory floats its outputs and the host takes N/A (float) control of FWH0-FWH3. IDSEL ADDR MSIZE M50FLW080A, M50FLW080B Description DATA TAR SYNC TAR Table AI08434B 15/53 ...
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... M50FLW080A, M50FLW080B Table 8. LPC Bus Read Field Definitions (1-Byte) Clock Clock Cycle Cycle Field Number Count 1 1 START CYCTYPE DIR 3-10 8 ADDR 11 1 TAR 12 1 TAR 13-14 2 WSYNC 15 1 RSYNC 16-17 2 DATA 18 1 TAR 19 1 TAR Figure 9. LPC Bus Read Waveforms (1-Byte) CLK ...
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... START ADDR DATA + DIR M50FLW080A, M50FLW080B Description Table 5. shows the TAR SYNC TAR AI04430 V DQ7-DQ0 PP Don't Care Data Output Data Input CC PPH Don't Care Hi-Z Don't Care Hi-Z 17/53 ...
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... M50FLW080A, M50FLW080B COMMAND INTERFACE All Bus Write operations to the device are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings, and verifies the correct execution of the Program and Erase commands. The Pro- ...
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... Status Register will indicate the error. During the Block Erase operation the memory will only accept the Read Status Register and Pro- gram/Erase Suspend commands. All other com- mands are ignored. M50FLW080A, M50FLW080B 23., for a suggested flowchart on using Table 18.. , otherwise the result is uncertain. ...
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... M50FLW080A, M50FLW080B See Figure 27., for a suggested flowchart on using the Block Erase command. Typical Block Erase times are given in Table 18.. Sector Erase Command. The command is used to erase a Uniform 4-KByte Sec- tor, setting all of the bits to ‘1’. All previous data in the sector are lost. ...
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... A1 A2 Data1 80h X 10h 20h BA D0h 32h SA D0h 50h B0h D0h 00h 01h 60h 2Fh C0h Table 5. (for LPC mode) M50FLW080A, M50FLW080B (1) 3rd 4th Data Addr Data Addr (Read (Read (Read (Read Data2) Addr3) Data3) Addr4) (Status (Status (X) (X) Reg) Reg) ...
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... M50FLW080A, M50FLW080B STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. The bits in the Status Register convey specific in- formation about the progress of the operation. To read the Status Register, the Read Status Reg- ister command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued ...
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... Interface only) Erase failure due to failed cell(s) in block or sector Note: 1. For Program operations during Erase Suspend, the SR6 bit is ‘1’, otherwise the SR6 bit is ‘0’. M50FLW080A, M50FLW080B since the last Clear Status Register command or hardware reset. When the Block/Sector Protection Status bit is ‘ ...
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... M50FLW080A, M50FLW080B FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS When the Firmware Hub Interface/Low Pin Count is selected, several additional registers can be ac- cessed. These registers control the protection sta- tus of the Blocks/Sectors, read the General Purpose Input pins and identify the memory using the manufacturer code ...
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... Purpose Input pins should remain constant throughout the whole Bus Read cycle. Manufacturer Code Register Reading the Manufacturer Code Register returns the value 20h, which is the Manufacturer Code for STMicroelectronics. This register is read-only. Writing to it has no effect. M50FLW080A, M50FLW080B (1) Function (1) Function 25/53 ...
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... M50FLW080A, M50FLW080B PROGRAM AND ERASE TIMES The Program and Erase times are shown in 18.. Table 18. Program and Erase Times Parameter Byte Program Double Byte Program Quadruple Byte Program Block Program (2) Sector Erase (4 KBytes) Block Erase (64 KBytes) Chip Erase Program/Erase Suspend to Program pause ...
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... JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter R2=500 ) M50FLW080A, M50FLW080B Min. Max. Unit –65 150 °C 1 °C See note V + 0.6 – ...
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... M50FLW080A, M50FLW080B DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 20. Operating Conditions Symbol V Supply Voltage ...
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... Note: 1. Sampled only, not 100% tested. 2. See PCI Specification 25° 1MHz DEVICE UNDER TEST 0.1µF 0.1µ includes JIG capacitance Test Condition M50FLW080A, M50FLW080B 1.5V AI01417 16. 16.7k AI08430 Min Max Unit 29/53 ...
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... M50FLW080A, M50FLW080B Table 24. DC Characteristics Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V (INIT) INIT Input High Voltage IH V (INIT) INIT Input Low Voltage IL (2) Input Leakage Current I LI IC, IDx Input Leakage I LI2 Current IC, IDx Input Pull Low R IL ...
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... Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. tCYC tHIGH tLOW Test Condition Min Min Min Min peak to peak Max M50FLW080A, M50FLW080B 0 p-to-p (minimum) AI03403 Value Unit ...
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... M50FLW080A, M50FLW080B Figure 15. FWH/LPC Interface AC Signal Timing Waveforms CLK FWH0-FWH3/ LAD0-LAD3 tCHFH tFLCH FWH4 START CYCLE Table 26. FWH/LPC Interface AC Signal Timing Characteristics PCI Symbol Symbol t t CLK to Data Out CHQV val CLK to Active ( CHQX (Float to Active Delay) CLK to Inactive ...
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... LFRAME Low t RP High to Write Enable or Output PHWL t Enable Low PHGL Note: 1. See Chapter 4 of the PCI Specification. Test Condition (1) Rising edge only FWH/LPC Interface only A/A Mux Interface only M50FLW080A, M50FLW080B tPHWL, tPHGL, tPHFL Ai09705 Value Min 100 Min 50 Min 30 Min 50 Unit ...
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... M50FLW080A, M50FLW080B Figure 17. A/A Mux Interface Read AC Waveforms A0-A10 ROW ADDR VALID tAVCL tCLAX RC G DQ0-DQ7 W tPHAV RP Table 28. A/A Mux Interface Read AC Characteristics Symbol Parameter t Read Cycle Time AVAV t Row Address Valid to RC Low AVCL t RC Low to Row Address Transition CLAX t Column Address Valid to RC high ...
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... tCLAX tAVCH tCHAX tCHWH tVPHWH tDVWH tWHDX D IN1 D IN2 Test Condition Low PP < 3.6V). PP M50FLW080A, M50FLW080B Read Status Ready to write Register Data another command tWHGL tQVVPL VALID SRD Value Min 100 Min 50 Min 5 Min 50 Min 50 ...
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... M50FLW080A, M50FLW080B PACKAGE MECHANICAL Figure 19. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline Note: Drawing is not to scale. 36/ 0.51 (.020) 1.14 (.045 PLCC-A ...
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... M50FLW080A, M50FLW080B inches Typ Min 0.125 0.060 0.015 0.013 0.026 0.485 0.447 0.188 0.300 – 0.585 0.547 0.238 0.400 – 0.050 – 0.000 0.035 – 32 Max 0.140 0.095 – 0.021 0.032 0.004 ...
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... M50FLW080A, M50FLW080B Figure 20. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline 1 N/2 TSOP-a Note: Drawing is not to scale. Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data Symbol Typ 0.500 38/ DIE ...
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... DIE C millimeters Min Max 1.200 0.050 0.150 0.950 1.050 0.170 0.270 0.100 0.210 0.100 19.800 20.200 18.300 18.500 – – 9.900 10.100 0.500 0.700 0 5 M50FLW080A, M50FLW080B inches Typ Min – Max ...
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... M50FLW080A, M50FLW080B PART NUMBERING Table 33. Ordering Information Scheme Example:M50FLW080 Device Type M50 = Flash Memory for PC BIOS Architecture FL = Firmware Hub/Low Pin Count Interface Operating Voltage 3.0 to 3.6V CC Device Function 080 = 8 Mbit (x8), Uniform Blocks and Sectors Array Matrix 4KByte top sectors + 4KByte bottom sectors ...
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... APPENDIX A. BLOCK AND SECTOR ADDRESS TABLE Table 34. M50FLW080A Block, Sector and Lock Register Addresses Block Block Sector Address Size No and Size Range (KByte) Type (KByte) FF000h- 4 FFFFFh FE000h- 4 FEFFFh FD000h- 4 FDFFFh FC000h- 4 FCFFFh FB000h- 4 FBFFFh FA000h- 4 FAFFFh F9000h- 4 F9FFFh F8000h- 4 F8FFFh ...
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... M50FLW080A, M50FLW080B Block Block Sector Address Size No and Size Range (KByte) Type (KByte) D0000h DFFFFh (Main) C0000h CFFFFh (Main) B0000h BFFFFh (Main) A0000h AFFFFh (Main) 90000h 9FFFFh (Main) 80000h 8FFFFh (Main) 70000h 7FFFFh (Main) ...
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... FBF9002 64 40 FBF8002 64 39 FBF7002 64 38 FBF6002 64 37 FBF5002 64 36 FBF4002 64 35 FBF3002 34 FBF2002 33 FBF1002 32 FBF0002 M50FLW080A, M50FLW080B Block Sector Address Sector No and Size Range No Type (KByte) E0000h- 14 EFFFFh (Main) D0000h- 13 DFFFFh (Main) C0000h- 12 CFFFFh (Main) B0000h- 11 BFFFFh (Main) A0000h- ...
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... M50FLW080A, M50FLW080B Block Block Sector Address Size No and Size Range (KByte) Type (KByte) 1F000h- 4 1FFFFh 1E000h- 4 1EFFFh 1D000h- 4 1DFFFh 1C000h- 4 1CFFFh 1B000h- 4 1BFFFh 1A000h- 4 1AFFFh 19000h- 4 19FFFh 18000h- 4 18FFFh 1 64 (Main) 17000h- 4 17FFFh 16000h- 4 16FFFh 15000h- 4 15FFFh 14000h- 4 14FFFh 13000h- 4 13FFFh ...
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... Error ( Program to Protected Block/Sector Error (1, 2) invalid) and SR4 (Program Error) can be made after each Program op- PP M50FLW080A, M50FLW080B Program command: – Write 40h or 10h – Write Address and Data (memory enters read status state after the Program command) do: – ...
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... M50FLW080A, M50FLW080B Figure 23. Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only) Start Write 40h or 10h Write Start Address and 2/4 Data Bytes (3) Read Status Register SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End Note Status check of SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation by following the correct PP command sequence ...
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... Loop Invalid Error ( Program Error (1, 2) M50FLW080A, M50FLW080B Quadruple Byte Program command: – write 30h – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) – write Address 3 & Data 3 (3) – write Address 4 & Data 4 (3) ...
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... M50FLW080A, M50FLW080B Figure 25. Program Suspend and Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register SR7 = 1 YES SR2 = 1 YES Write a read Command Read data from another address Write D0h Program Continues Note error is found, the Status Register must be cleared before further Program/Erase operations. ...
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... Invalid Error (1) NO Command Sequence Error (1) NO Erase Error (1) M50FLW080A, M50FLW080B Chip Erase command: – write 80h – write 10h (memory enters read Status Register after the Chip Erase command) do: – read Status Register while SR7 = 0 If SR3 = invalid error: – ...
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... M50FLW080A, M50FLW080B Figure 27. Sector/Block Erase Flowchart and Pseudo Code Start Write 20h/32h Write Block/Sector Address and D0h Read Status Register SR7 = 1 YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES FWH/LPC Interface SR1 = 0 Only YES End Note the Block Erase command is used on a block that is split into 4KByte sectors, each of the 16 sectors of the block should be un- locked before performing the erase operation ...
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... Program Write D0h Erase Continues NO NO Erase Complete Write FFh Read Data M50FLW080A, M50FLW080B Program/Erase Suspend command: – write B0h – write 70h do: – read Status Register while SR7 = 0 If SR6 = 0, Erase completed Program/Erase Resume command: – write D0h to resume erase – ...
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... M50FLW080A, M50FLW080B REVISION HISTORY Table 36. Document Revision History Date Version 02-Feb-2004 0.1 21-Apr-2004 0.2 24-May-2004 1.0 18-Aug-2004 2.0 52/53 Revision Details First Issue TSOP32 package added First public release Pins 2 and 5 of the TSOP32 Connections illustration corrected ...
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