74LVC2G126DC,125 NXP Semiconductors, 74LVC2G126DC,125 Datasheet - Page 9

• Manufacturer Part Number: 74LVC2G126DC,125
• Description: IC BUS BUFF DVR TRI-ST DL 8VSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC2G126DC,125

• Package / Case: US8, 8-VSSOP
• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: LVC
• Number Of Channels Per Chip: 2
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.65 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 32 mA
• Input Bias Current (max): 40 uA
• Low Level Output Current: 32 mA
• Maximum Power Dissipation: 300 mW
• Minimum Operating Temperature: - 40 C
• Output Current: 50 mA
• Output Type: 3-State
• Output Voltage: 6.5 V
• Propagation Delay Time: 2.8 ns (Typ) @ 2.7 V or 2.4 ns (Typ) @ 3.3 V or 1.9 ns (Typ) @ 5 V
• Number Of Lines (input / Output): 2 / 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVC2G126DC-G; 74LVC2G126DC-G; 935274583125

NXP Semiconductors
12. Waveforms
Table 9.
74LVC2G126
Product data sheet
Supply voltage
V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
Fig 7.
Fig 8.
CC
Measurement points are given in
Logic levels: V
Measurement points are given in
Logic levels: V
The data input (nA) to output (nY) propagation delays
3-state enable and disable times
Measurement points
OL
OL
and V
and V
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
nOE input
OH
OH
output
output
are typical output voltage levels that occur with the output load.
are typical output voltage levels that occur with the output load.
nY output
nA input
Input
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
M
GND
GND
V
Table
V
Table
V
OH
CC
OL
V
All information provided in this document is subject to legal disclaimers.
I
CC
CC
CC
9.
9.
GND
V
V
OH
OL
V
Rev. 9 — 13 September 2010
I
enabled
V
outputs
M
t
PLZ
t
PHZ
V
M
Output
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
V
V
M
X
M
V
Y
t
PHL
CC
CC
CC
disabled
outputs
t
PZL
t
PZH
V
V
V
V
V
V
mna230
t
X
OL
OL
OL
OL
OL
PLH
Dual bus buffer/line driver; 3-state
V
+ 0.15 V
+ 0.15 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
M
V
M
outputs
enabled
mna949
74LVC2G126
V
V
V
V
V
V
© NXP B.V. 2010. All rights reserved.
Y
OH
OH
OH
OH
OH
− 0.15 V
− 0.15 V
− 0.3 V
− 0.3 V
− 0.3 V
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