74LVC2G126DC,125 NXP Semiconductors, 74LVC2G126DC,125 Datasheet - Page 10

IC BUS BUFF DVR TRI-ST DL 8VSSOP

74LVC2G126DC,125

Manufacturer Part Number
74LVC2G126DC,125
Description
IC BUS BUFF DVR TRI-ST DL 8VSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC2G126DC,125

Package / Case
US8, 8-VSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 32mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
Number Of Channels Per Chip
2
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Input Bias Current (max)
40 uA
Low Level Output Current
32 mA
Maximum Power Dissipation
300 mW
Minimum Operating Temperature
- 40 C
Output Current
50 mA
Output Type
3-State
Output Voltage
6.5 V
Propagation Delay Time
2.8 ns (Typ) @ 2.7 V or 2.4 ns (Typ) @ 3.3 V or 1.9 ns (Typ) @ 5 V
Number Of Lines (input / Output)
2 / 2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC2G126DC-G
74LVC2G126DC-G
935274583125

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVC2G126DC,125
Manufacturer:
NXP Semiconductors
Quantity:
2 900
NXP Semiconductors
Table 10.
74LVC2G126
Product data sheet
Supply voltage
V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
Fig 9.
CC
Test data is given in
Definitions for test circuit:
R
C
R
V
Test circuit for measuring switching times
L
L
T
EXT
Test data
= Load resistance.
= Load capacitance including jig and probe capacitance.
= Termination resistance should be equal to the output impedance Z
= External voltage for measuring switching times.
Table
Input
V
V
V
2.7 V
2.7 V
V
I
CC
CC
CC
10.
G
All information provided in this document is subject to legal disclaimers.
t
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
r
, t
f
V
Rev. 9 — 13 September 2010
I
R T
Load
C
30 pF
30 pF
50 pF
50 pF
50 pF
DUT
V
L
CC
V
O
R
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
L
C L
o
of the pulse generator.
V
mna616
EXT
R L
R L
V
t
open
open
open
open
open
PLH
Dual bus buffer/line driver; 3-state
EXT
, t
PHL
74LVC2G126
t
GND
GND
GND
GND
GND
PZH
, t
PHZ
© NXP B.V. 2010. All rights reserved.
t
2 × V
2 × V
6 V
6 V
2 × V
PZL
, t
CC
CC
CC
PLZ
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