ML4824-1 Fairchild Semiconductor, ML4824-1 Datasheet

no-image

ML4824-1

Manufacturer Part Number
ML4824-1
Description
The ML4824 is a controller for power factor corrected, switched mode power supplies
Manufacturer
Fairchild Semiconductor
Datasheet
Features
• Internally synchronized PFC and PWM in one IC
• Low total harmonic distortion
• Reduces ripple current in the storage capacitor between
• Average current, continuous boost leading edge PFC
• Fast transconductance error amp for voltage loop
• High efficiency trailing edge PWM can be configured for
• Average line voltage compensation with brownout
• PFC overvoltage comparator eliminates output
• Current fed gain modulator for improved noise immunity
• Overvoltage protection, UVLO, and soft start
ML4824
Power Factor Correction and PWM Controller
Combo
Block Diagram
15
2
4
3
7
8
6
5
9
the PFC and PWM sections
current mode or voltage mode operation
control
“runaway” due to load removal
I AC
V FB
V RMS
I SENSE
RAMP 1
RAMP 2
V DC
SS
DC I LIMIT
2.5V
V CC
50 A
8V
+
8V
VEA
VEAO
MODULATOR
1.25V
GAIN
16
3.5k
3.5k
+
+
IEA
IEAO
+
(-2 VERSION ONLY)
1
OSCILLATOR
+
POWER FACTOR CORRECTOR
2.5V
V FB
PULSE WIDTH MODULATOR
+
x 2
V IN OK
DUTY CYCLE
General Description
The ML4824 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching FETs,
and results in a power supply that fully complies with
IEC1000-2-3 specification. The ML4824 includes circuits
for the implementation of a leading edge, average current,
“boost” type power factor correction and a trailing edge,
pulse width modulator (PWM).
The device is available in two versions; the ML4824-1 (f
= f
switching frequency of the PWM allows the user to design
with smaller output components while maintaining the best
operating frequency for the PFC. An over-voltage compara-
tor shuts down the PFC section in the event of a sudden
decrease in load. The PFC section also includes peak current
limiting and input voltage brown-out protection. The PWM
section can be operated in current or voltage mode at up to
250kHz and includes a duty cycle limit to prevent trans-
former saturation.
LIMIT
PFC
2.7V
1V
–1V
) and the ML4824-2 (f
PFC I LIMIT
+
OVP
+
+
DC I LIMIT
V CCZ
V CCZ
13.5V
PWM
www.fairchildsemi.com
UVLO
= 2 x f
R
R
R
S
S
S
Q
Q
Q
Q
Q
Q
REFERENCE
PFC
REV. 1.0.6 11/7/03
7.5V
). Doubling the
13
V CC
PWM OUT
PFC OUT
V REF
PWM
14
12
11

Related parts for ML4824-1

ML4824-1 Summary of contents

Page 1

... IEC1000-2-3 specification. The ML4824 includes circuits for the implementation of a leading edge, average current, “boost” type power factor correction and a trailing edge, pulse width modulator (PWM). The device is available in two versions; the ML4824 and the ML4824-2 (f PFC switching frequency of the PWM allows the user to design with smaller output components while maintaining the best operating frequency for the PFC ...

Page 2

... Positive supply (connected to an internal shunt regulator Buffered output for the internal 7.5V reference REF 15 V PFC transconductance voltage error amplifier input FB 16 VEAO PFC transconductance voltage error amplifier output 2 ML4824 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W) IEAO 1 16 VEAO SENSE 3 14 ...

Page 3

... VEAO = 3.75V NON INV INV Note ±0.5V OUT V = ±0.5V 1.5V IN OUT < V < 0.5V CCZ CC CCZ VEAO = 3.75V NON INV INV ML4824 Max. Units 0.3 V CCZ 500 mA 500 mA 1.5 µJ 150 °C 150 °C 260 ° ...

Page 4

... ML4824 Electrical Characteristics Unless otherwise specified 25mA Symbol Parameter Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio OVP Comparator Threshold Voltage Hysteresis PFC I Comparator LIMIT Threshold Voltage ...

Page 5

... Hours J V > 4.0V IEAO V < 1.2V IEAO I = -20mA OUT I = -100mA OUT I = 10mA OUT 20mA OUT I = 100mA OUT C = 1000pF L ML4824-1 ML4824 -20mA OUT I = -100mA OUT I = 10mA OUT 20mA OUT I = 100mA OUT C = 1000pF L ) CCZ 25mA < I < 55mA CC Load, Temp ...

Page 6

... ML4824 Typical Performance Characteristics 250 200 150 100 (V) Voltage Error Amplifier (VEA) Transconductance (g 16 IEAO VEAO V FB VEA IEA 3.5k 15 – + 2.5V + – GAIN V RMS MODULATOR 4 3.5k I SENSE 3 RAMP 250 200 150 100 Current Error Amplifier (IEA) Transconductance (g ...

Page 7

... PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4824-1 runs at the same frequency as the PFC. The PWM section of the ML4824-2 runs at twice the frequency of the PFC, which allows the use of smaller PWM output magnetics and fi ...

Page 8

... PFC will not restart until the voltage at V set at a level where the active and passive external power components and the ML4824 are within their safe operating pin SENSE voltages, but not so low as to interfere with the boost voltage regulation loop. Error Amplifi ...

Page 9

... Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing (at the PFC frequency in the ML4824-1, and at twice the PFC frequency in the ML4824-2). The PWM is capable of current-mode or voltage mode operation. In current-mode ...

Page 10

... CC The maximum allowable I able design. (6) The ML4824 should be locally bypassed with a 10nF and ceramic capacitor. In most applications, an electrolytic capacitor of between 100 F and 330 F is also required DELAY across the part, both for filtering and as part of the start-up bootstrap circuitry. ...

Page 11

... PFC’s output ripple voltage can be reduced by as much as 30% using this method. SW2 SW1 C1 RAMP DFF + VSW1 R Q – CLK SW2 SW1 C1 RAMP VEAO DFF CMP VSW1 + R Q – CLK VEAO TIME TIME VEAO TIME TIME ML4824 11 ...

Page 12

... R7B C6 178k 1nF 16 VEAO REF C15 12 10nF PFC OUT 11 PWM OUT 10 D8 GND 1A, 20V D10 LIMIT 1A, 20V ML4824 C17 R6 220pF R10 41.2k 6.2k PRODUCT SPECIFICATION Q2 IRF830 D5 600V D7 L2 D11 15V 33 H MBR2545CT T2 C24 C21 600V 1800 F R24 1.2k ...

Page 13

... Mechanical Dimensions 16 PIN 0.02 MIN (0.50 MIN) 0.055 - 0.065 (4 PLACES) (1.40 - 1.65) 0.170 MAX (4.32 MAX) 0.016 - 0.022 0.125 MIN (0.40 - 0.56) (3.18 MIN) REV. 1.0.6 11/7/03 inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) SEATING PLANE ML4824 0.008 - 0.012 (0.20 - 0.31) 13 ...

Page 14

... ML4824 Mechanical Dimensions 0.400 - 0.414 (10.16 - 10.52) 16 PIN 0.024 - 0.034 0.050 BSC (0.61 - 0.86) (1.27 BSC) (4 PLACES) 0.012 - 0.020 0.090 - 0.094 (0.30 - 0.51) (2.28 - 2.39) 14 inches (millimeters) Package: S16W 16-Pin Wide SOIC 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) 0.095 - 0.107 (2.41 - 2.72 0.022 - 0.042 0.005 - 0.013 SEATING PLANE (0.56 - 1.07) (0.13 - 0.33) PRODUCT SPECIFICATION 0.009 - 0.013 (0 ...

Page 15

... ML4824CP1 1 x PFC ML4824CP2 2 x PFC ML4824CS1 1 x PFC ML4824CS2 2 x PFC ML4824IP1 1 x PFC ML4824IS1 1 x PFC ML4824IS2 2 x PFC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN ...

Related keywords