IR3897MTRPBF International Rectifier, IR3897MTRPBF Datasheet - Page 31

• Manufacturer Part Number: IR3897MTRPBF
• Description: 4A Highly Integrated Single-Input Voltage, Synchronous Buck Regulator in a PQFN package.
• Manufacturer: International Rectifier

Specifications of IR3897MTRPBF

• Part Status: Active and Preferred
• Package: PQFN / 4 x 5
• Circuit: Single Output
• Iout (a): 4
• Switch Freq (khz): 0 - 1500
• Input Range (v): 1.0 - 16
• Output Range (v): 0.5 - 12
• Pbf: PbF Option Available

computations related to the compensation. The small
signal value may be obtained from the manufacturer’s
datasheets, design tools or SPICE models. Alternatively,
they may also be inferred from measuring the power
stage transfer function of the converter and measuring
the double pole frequency F
to compute the small signal C
These result to:
Select crossover frequency F
Since F
pole and zeros.
Detailed calculation of compensation Type III:
Desired Phase Margin Θ = 70°
Select:
Select C
Calculate R
Select R
C
C
2
F
F
F
3
LC
ESR
s

/2=300 kHz

=20.5 kHz
2 *
LC
=5.3 MHz
R
2 *
4
3

<F
= 2.2nF.
= 3.01 kΩ:
3

F

0
F
F
3
P
<Fs/2<F
F
, C
F
Z
1
1
Z
2
2 *
31
P
Z
1
2

3
1

3

and C
*

*
F
F
0.5*
R
R
P
F
F
o
3
3
o
3
o
FEBRUARY 02, 2012 |DATA SHEET | Rev 3.2
ESR
;

C V
;
*
1 sin
1 sin
2
C
C
, Type III is selected to place the
1 sin
1 sin
4
0.5*
F
:
L C V


2
*
3


o
Z


2
*
in
176 pF, Select:
F

4.9 nF, Select:
s
LC
o
0
=120 kHz
o



*
and using equation (17)


10.6 kHz and
.
300 kHz

osc

680.6 kHz
21.2 KHz
;
R
3
Single‐Input Voltage, Synchronous Buck Regulator


3.08 Ω
C
C
2
3
k


120 pF
10 nF
- 31 -
4A Highly Integrated SupIRBuck
Calculate R
Select R
Setting the Power Good Threshold
In this design IR3897 is used in normal (non‐tracking,
non‐sequencing) mode, therefore the PGood thresholds are
internally set at 90% and 120% of Vref. At startup as soon as
Vsns voltage reaches 0.9*0.5V=0.45V (Fig. 15), after 1.28ms
delay, PGood signal is asserted. As long as the Vsns voltage
is between the threshold range, Enable is high, and no fault
happens, the PGood remains high.
The following formula can be used to set the threshold.
V
The PGood is an open drain output. Hence, it is necessary to
use a pull up resistor, R
of the pull‐up resistor must be chosen such as to limit the
current flowing into the PGood pin to less than 5mA when
the output voltage is not in regulation. A typical value used
is 49.9kΩ.
OVP comparator also uses Vsns signal for over Voltage
dectection.With above values for R7 and R8, OVP trip point
(Vout_
Vref Bypass Capacitor
A minimum value of 100pF bypass capacitor is recommended
to be placed between Vref and Gnd pins.This capacitor should
be placed as close as possible to Vref pin..
Vout
outPGood_Th
R
6
R

4
_

V V
OVP)
OVP
5
o
2 *
= 3.32 kΩ:
V
R
R

-
is
ref
R
can be taken as 90% of Vout. Choose R7=3.32KΩ:
4
8
8

, R
5
ref


Vref
C

5
1
Vout
2.37
and R
4
*
2 *
*

R R
F
5
*1.2 * ( 7
;
P
K
Vref
PGood Th
C
2
6
1
;
:
4

6
PG
*

R
, from PGood pin to Vcc. The value
F
_
* 0.9 * 7
4
R
2.37 kΩ Select:
Z
2


-
106 Ω, Select:

Vref
R
R
4
R
;
8) / 8 1.44
TM
R
* 0.9
5
R

3.41 kΩ,

IR3897
R
R
6
V
4
(34)


PD‐97663
2.37 kΩ
100 Ω
(35)