IR3897MTRPBF International Rectifier, IR3897MTRPBF Datasheet - Page 24

• Manufacturer Part Number: IR3897MTRPBF
• Description: 4A Highly Integrated Single-Input Voltage, Synchronous Buck Regulator in a PQFN package.
• Manufacturer: International Rectifier

Specifications of IR3897MTRPBF

• Part Status: Active and Preferred
• Package: PQFN / 4 x 5
• Circuit: Single Output
• Iout (a): 4
• Switch Freq (khz): 0 - 1500
• Input Range (v): 1.0 - 16
• Output Range (v): 0.5 - 12
• Pbf: PbF Option Available

SOFT START/SOFT‐STOP (S_CTRL)
Soft‐stop function can make output voltage discharge
gradually. To enable this function, S_Ctrl is kept low first
when EN goes high. Then S_Ctrl is pulled high to cross the
logic level threshold (typ. 2V), the internal soft‐start ramp
is initiated. So Vo follows Intl_SS to ramp up until it
reaches its steady state. In soft‐stop process, S_Ctrl needs
to be pulled low before EN goes low. After S_Ctrl goes
below its threshold, a decreasing ramp is generated at
Intl_SS with the same slope as in soft‐start ramp. Vo
follows this ramp to discharge softly until shutdown
completely. Figure 19 shows the timing diagram of S_Ctrl
controlled soft‐start and soft‐stop.
If the falling edge of Enable signal asserts before S_Ctrl
falling edge, the converter is still turned off by Enable.
Both gate drivers are turned off immediately and Vo
discharges to zero. Figure 20 shows the timing diagram
of Enable controlled soft‐start and soft‐stop. Soft stop
feature ensures that Vout discharges and also regulates
the current precisely to zero with no undershoot.
Figure 18: Timing Diagram for OVP in non‐tracking mode
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FEBRUARY 02, 2012 |DATA SHEET | Rev 3.2
Single‐Input Voltage, Synchronous Buck Regulator
- 24 -
4A Highly Integrated SupIRBuck
MINIMUM ON TIME CONSIDERATIONS
The minimum ON time is the shortest amount of time for
Ctrl FET to be reliably turned on. This is very critical
parameter for low duty cycle, high frequency applications.
Conventional approach limits the pulse width to prevent
noise, jitter and pulse skipping. This results to lower closed
loop bandwidth.
IR has developed a proprietary scheme to improve and
enhance minimum pulse width which utilizes the benefits
of voltage mode control scheme with higher switching
frequency, wider conversion ratio and higher closed loop
bandwidth, the latter results in reduction of output
capacitors.
Enable
S_Ctrl
Vout
Enable
S_Ctrl
Vout
_SS
Intl
_SS
Intl
0
0
0
0
0
0
0
Figure 20: Timing Diagram for Enable controlled
0
Figure 19: Timing Diagram for S_Ctrl controlled
0.65V
0.15V
0.65V
0.15V
1.2V
Soft Start/Shutdown
Soft Start/Soft Stop
TM
IR3897
1.0V
PD‐97663
0.65V
0.15V