IR3897MTRPBF International Rectifier, IR3897MTRPBF Datasheet - Page 21

• Manufacturer Part Number: IR3897MTRPBF
• Description: 4A Highly Integrated Single-Input Voltage, Synchronous Buck Regulator in a PQFN package.
• Manufacturer: International Rectifier

Specifications of IR3897MTRPBF

• Part Status: Active and Preferred
• Package: PQFN / 4 x 5
• Circuit: Single Output
• Iout (a): 4
• Switch Freq (khz): 0 - 1500
• Input Range (v): 1.0 - 16
• Output Range (v): 0.5 - 12
• Pbf: PbF Option Available

FEED‐FORWARD
Feed‐Forward (F.F.) is an important feature, because it can
keep the converter stable and preserve its load transient
performance when Vin varies in a large range. In IR3897,
F.F. function is enabled when Vin pin is connected to PVin
pin. In this case, the internal low dropout (LDO) regulator is
used. The PWM ramp amplitude (Vramp) is proportionally
changed with Vin to maintain Vin/Vramp almost constant
throughout Vin variation range (as shown in Fig. 10). Thus,
the control loop bandwidth and phase margin can be
maintained constant. Feed‐forward function can also
minimize impact on output voltage from fast Vin change.
The maximum Vin slew rate is within 1V/µs.
If an external bias voltage is used as Vcc, Vin pin should be
connected to Vcc/LDO_Out pin instead of PVin pin. Then
the F.F. function is disabled. A re‐calculation of control
loop parameters is needed for re‐compensation.
SMART LOW DROPOUT REGULATOR (LDO)
IR3897 has an integrated low dropout (LDO) regulator
which can provide gate drive voltage for both drivers.
In order to improve overall efficiency over the whole load
range, LDO voltage is set to 6.4V (typ.) at mid‐ or heavy
load condition to reduce Rds(on) and thus MOSFET
conduction loss; and it is reduced to 4.4 (typ.) at light load
condition to reduce gate drive loss.
The smart LDO can select its output voltage according to
the load condition by sensing switch node (SW) voltage. At
light load condition when part of the inductor current
flows in the reverse direction (DCM=1), V
falling edge in a switching cycle. If this case happens for
consecutive 256 switching cycles, the smart LDO reduces
its output to 4.4. If in any one of the 256 cycles, Vsw < 0 on
LDrv falling edge, the counter is reset and LDO voltage
doesn’t change. On the other hand, if Vsw < 0 on LDrv
falling edge (DCM=0), LDO output is increased to 6.4V. A
hysteresis band is added to Vsw comparison to avoid
Figure 10: Timing Diagram for Feed‐Forward (F.F.) Function
21
FEBRUARY 02, 2012 |DATA SHEET | Rev 3.2
Single‐Input Voltage, Synchronous Buck Regulator
SW
> 0 on LDrv
- 21 -
4A Highly Integrated SupIRBuck
chattering. Figure 11 shows the timing diagram. Whenever
device turns on, LDO always starts with 6.4V, then goes to
4.4V/6.4V depending upon the load condition
OUTPUT VOLTAGE TRACKING AND SEQUENCING
IR3897 can accommodate user programmable tracking
and/or sequencing options using Vp, Vref, Enable, and
Power Good pins. In the block diagram presented on page
3, the error‐amplifier (E/A) has been depicted with three
positive inputs. Ideally, the input with the lowest voltage
is used for regulating the output voltage and the other
two inputs are ignored. In practice the voltage of the other
two inputs should be about 200mV greater than the
low‐voltage input so that their effects can completely
be ignored. Vp is internally biased to 3.3V via a high
impedance path. For normal operation, Vp and Vref is
left floating (Vref should have a bypass capacitor).
Therefore, in normal operating condition, after Enable
goes high, the internal soft‐start (Intl_SS) ramps up the
output voltage until Vfb (voltage of feedback/Fb pin)
reaches about 0.5V. Then Vref takes over and the output
voltage is regulated.
Tracking‐mode operation is achieved by connecting Vref to
GND. Then, while Vp=0, Enable is taken above its threshold
so that the soft‐start circuit generates Intl_SS signal. After
the Intl_SS signal reaches the final value (refer to Fig. 5c),
ramping up the Vp input will ramp up the output voltage.
In tracking mode, Vfb always follows Vp which means Vout
is always proportional to Vp voltage (typical for DDR/Vtt
rail applications). The effective Vp variation range is
0V~1.2V.
In sequencing mode of operation (simultaneous or
ratiometric), Vref is left floating and Vp is kept to ground
level until Intl_SS signal reaches the final value. Then Vp is
ramped up and Vfb follows Vp. When Vp>0.5V the error‐
LDO
Vcc/
IL
0
0
Figure 11: Time Diagram for SmartLDO
6.4V
256/Fs
...
...
TM
4.4V
...
IR3897
PD‐97663
6.4V
...