TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 43

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
Table 2-3 Operation Modes and Conditions
Single clock
Dual clock
2.3.6
2.3.6.1
Operation mode
Operation Mode Control
RESET
NORMAL1
IDLE1
IDLE0
STOP
NORMAL2
IDLE2
SLOW2
SLOW1
SLEEP1
SLEEP0
STOP
(1)
(2)
The STOP mode is controlled by system control register 1 (SYSCR1) and the STOP mode release signals.
STOP mode
states are maintained:
by the RESET pin, a power-on reset and a reset by the voltage detection circuits. When a reset is released,
the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active.
The STOP mode is started by setting SYSCR1<STOP> to "1". In the STOP mode, the following
The STOP mode is released by the following STOP mode release signals. It is also released by a reset
Start the STOP mode
Release the STOP mode
1. Both the high-frequency and low-frequency clock oscillation circuits stop oscillation and all
2. The data memory, the registers and the program status word are all held in the states in effect
3. The prescaler and the divider of the timing generator are cleared to "0".
4. The program counter holds the address of the instruction 2 ahead of the instruction (e.g., [SET
1. Release by the STOP pin
2. Release by key-on wakeup
3. Release by the voltage detection circuits
Oscillation
Oscillation
High-fre-
quency
internal operations are stopped.
before STOP mode was started. The port output latch is determined by the value of
SYSCR1<OUTEN>.
(SYSCR1).7]) which started the STOP mode.
Stop
Stop
Oscillation circuit
Oscillation
Low-fre-
quency
Stop
Stop
Operate with
Operate with
Operate with
the high fre-
the low fre-
the low fre-
CPU core
Operate
quency
quency
quency
Reset
Stop
Stop
Stop
Page 27
the high / low
Operate with
Operate with
Operate with
the low fre-
the low fre-
Watchdog
frequency
Operate
quency
quency
Reset
timer
Stop
Stop
Stop
Time base
Operate
Operate
Reset
timer
Stop
Stop
converter
Operate
Operate
Reset
Stop
Stop
AD
Other periph-
eral circuits
Operate
Operate
Reset
Stop
Stop
TMP89FS60
Machine cy-
1 / fcgck [s]
1 / fcgck [s]
cle time
4/ fs [s]
−
−