TMP86xy45UG Toshiba, TMP86xy45UG Datasheet - Page 88

• Manufacturer Part Number: TMP86xy45UG
• Manufacturer: Toshiba

Specifications of TMP86xy45UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 8
• Ram Size: 256
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: -
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: -
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 2.7 to 5.5

Example :Setting the timer mode with source clock fc/2
TC4CR<TC4S>
TTREG3
(Lower byte)
TTREG4
(Upper byte)
INTTC4 interrupt request
8.3.5 16-Bit Timer Mode (TC3 and 4)
Table 8-6 Source Clock for 16-Bit Timer Mode
Internal
source clock
Counter
DV7CK = 0
(fc = 16.0 MHz)
NORMAL1/2, IDLE1/2 mode
fc/2
fc/2
fc/2
fc/2
able to form a 16-bit timer.
timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter continues counting. Program the upper byte and lower byte in this order in
the timer register. (Programming only the upper or lower byte should not be attempted.)
11
7
5
3
In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad-
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
Note 3: j = 3, 4
?
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected
operation may not be obtained.
Figure 8-6 16-Bit Timer Mode Timing Chart (TC3 and TC4)
?
Source Clock
DV7CK = 1
0
fs/2
fc/2
fc/2
fc/2
n
m
3
7
5
3
LDW
DI
SET
EI
LD
LD
LD
1
2
SLOW1/2,
SLEEP1/2
(TTREG3), 927CH
(EIRH). 1
(TC3CR), 13H
(TC4CR), 04H
(TC4CR), 0CH
mode
fs/2
–
–
–
3
3
Match
detect
7
mn-1
fc = 16 MHz
Hz, and generating an interrupt 300 ms later
Page 77
128 µs
500 ns
8 µs
2 µs
mn
0
Resolution
Counter
clear
: Sets the timer register (300 ms
: Enables INTTC4 interrupt.
:Sets the operating cock to fc/2
: Sets the 16-bit timer mode (upper byte).
: Starts the timer.
(lower byte).
1
fs = 32.768 kHz
PDOj
244.14 µs
2
,
PWMj
–
–
–
, and
Match
detect
mn-1
PPGj
fc = 16 MHz
mn
524.3 ms
131.1 ms
32.8 ms
7
pins may output a pulse.
8.39 s
÷
, and 16-bit timer mode
0
2
7
/fc = 927CH).
Counter
clear
Repeated Cycle
1
2
fs = 32.768 kHz
TMP86C845UG
16 s
–
–
–
0