TMP86xy45UG Toshiba, TMP86xy45UG Datasheet - Page 82

• Manufacturer Part Number: TMP86xy45UG
• Manufacturer: Toshiba

Specifications of TMP86xy45UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 8
• Ram Size: 256
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: -
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: -
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 2.7 to 5.5

Example :Setting the timer mode with source clock fc/2
8.3 Function
8.3.1 8-Bit Timer Mode (TC3 and 4)
Table 8-4 Source Clock for TimerCounter 3, 4 (Internal Clock)
bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16-
bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter,
16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
DV7CK = 0
fc/2
The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8-
(TimerCounter4, fc = 16.0 MHz)
NORMAL1/2, IDLE1/2 mode
fc/2
fc/2
fc/2
11
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is
cleared. After being cleared, the up-counter restarts counting.
[Hz]
7
5
3
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
Note 3: j = 3, 4
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation
may not be obtained.
Source Clock
DV7CK = 1
fs/2
fc/2
fc/2
fc/2
3
[Hz]
7
5
3
LD
DI
SET
EI
LD
LD
(TTREG4), 0AH
(EIRH). 1
(TC4CR), 00010000B
(TC4CR), 00011000B
SLOW1/2,
SLEEP1/2
fs/2
mode
3
–
–
–
[Hz]
7
fc = 16 MHz
Hz and generating an interrupt 80 µs later
Page 71
500 ns
128 µs
8 µs
2 µs
Resolution
: Sets the timer register (80 µs
: Enables INTTC4 interrupt.
: Sets the operating cock to fc/2
: Starts TC4.
fs = 32.768 kHz
PDOj, PWMj
244.14 µs
–
–
–
and
PPGj
fc = 16 MHz
÷
127.5 µs
32.6 ms
pins may output pulses.
510 µs
2.0 ms
2
7
, and 8-bit timer mode.
7
/fc = 0AH).
Repeated Cycle
fs = 32.768 kHz
TMP86C845UG
62.3 ms
–
–
–