TMP86xy45UG Toshiba, TMP86xy45UG Datasheet - Page 103

• Manufacturer Part Number: TMP86xy45UG
• Manufacturer: Toshiba

Specifications of TMP86xy45UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 8
• Ram Size: 256
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: -
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: -
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 2.7 to 5.5

9.3 Function
SIOSR<SEF>
SO pin
SIOSR<TXF>
SIOCR1<SIOS>
SIOSR<SIOF>
SCK pin outout
INTSIO
interrupt
request
SIOTDB
(2)
(3)
Writing transmit
data A
Figure 9-6 Example of Internal Clock and MSB Transmit Mode
stops to “H” level by an automatic-wait function when all of the bit set in the SIOTDB has been
transmitted. Automatic-wait function is released by writing a transmit data to SIOTDB. Then, trans-
mit operation is restarted after maximum 1-cycle of serial clock.
SIOSR<TXF> “1”, the next data is continuously transferred after transmission of previous data.
SIOTDB before the shift operation of the next data begins.
tion is started. Then, INTSIO interrupt request is generated after SIOSR<TXERR> is set to “1”.
During the transmit operation
When data is written to SIOTDB, SIOSR<TXF> is cleared to “0”.
In internal clock operation, in case a next transmit data is not written to SIOTDB, the serial clock
When the next data is written to the SIOTDB before termination of previous 8-bit data with
In external clock operation, after SIOSR<TXF> is set to “1”, the transmit data must be written to
If the transmit data is not written to SIOTDB, transmit error occurs immediately after shift opera-
Stopping the transmit operation
There are two ways for stopping transmits operation.
A
• The way of clearing SIOCR1<SIOS>.
• The way of setting SIOCR1<SIOINH>.
When SIOCR1<SIOS> is cleared to “0”, transmit operation is stopped after all transfer of the
data is finished. When transmit operation is finished, SIOSR<SIOF> is cleared to “0” and
SO pin is kept in high level.
In external clock operation, SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is
set to “1” by beginning next transfer.
Transmit operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In this
case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initial-
ized.
A7
Writing transmit
data B
A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1
Start shift
operation
B
Page 92
Start shift
operation
B0
Automatic wait
Writing transmit
data C
C
C7
Start shift
operation
C6 C5 C4 C3 C2 C1 C0
Clearing SIOS
TMP86C845UG