TMP86xy45UG Toshiba, TMP86xy45UG Datasheet - Page 61

• Manufacturer Part Number: TMP86xy45UG
• Manufacturer: Toshiba

Specifications of TMP86xy45UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 8
• Ram Size: 256
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: -
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: -
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 2.7 to 5.5

5.3 Port P2 (P22 to P20)
5.3 Port P2 (P22 to P20)
Read only
(000AH)
(0002H)
P2PRD
nection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set
to “1”.
clock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports.
an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse.
ister should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable.
P2DR
R/W
Port P2 is a 3-bit input/output port.
It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator con-
During reset, the P2DR is initialized to “1”.
A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dual-
It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or
P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address.
When read the output latch data, the P2DR should be read and when read the terminal input data, the P2PRD reg-
Data input (P20PRD)
Data input (P21PRD)
Data input (P22PRD)
Data input (P20)
Data input (P21)
Data input (P22)
7
7
Control input
Data output
Data output
Data output
OUTEN
STOP
XTEN
6
6
fs
5
5
Output latch
Output latch
Output latch
D
D
D
4
4
Q
Q
Q
Figure 5-4 Port 2
3
3
Page 50
XTOUT
P22
P22
2
2
XTIN
P21
P21
Osc. enable
1
1
STOP
P20
INT5
P20
0
0
(Initial value: **** *111)
P20 (INT5, STOP)
P21 (XTIN)
P22 (XTOUT)
TMP86C845UG