TMP86xy45UG Toshiba, TMP86xy45UG Datasheet - Page 48

• Manufacturer Part Number: TMP86xy45UG
• Manufacturer: Toshiba

Specifications of TMP86xy45UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 8
• Ram Size: 256
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: -
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: -
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 2.7 to 5.5

3.3 Interrupt Source Selector (INTSEL)
3.4 Interrupt Sequence
Interrupt source selector
3.4.1 Interrupt acceptance processing is packaged as follows.
(003EH)
INTSEL
interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt
requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL reg-
ister must be set appropriately before interrupt requests are generated.
“0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after the
completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing
chart of interrupt acceptance processing.
Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the
The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL.
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
1. INT4 and (Don't set) share the interrupt source level whose priority is 15.
2.
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
INT5
a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any fol-
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt master
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vec-
e. The instruction stored at the entry address of the interrupt service program is executed.
7
-
lowing interrupt.
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Mean-
while, the stack pointer (SP) is decremented by 3.
tor table, is transferred to the program counter.
and INTADC share the interrupt source level whose priority is 16.
IL14ER
IL15ER
6
-
5
-
Selects INT4 or (Don't set)
Selects
INT5
4
-
or INTADC
3
-
Page 37
2
-
IL14ER
1
IL15ER
0: INT4
1: (Don't set)
0:
1: INTADC
0
INT5
(Initial value: **** **00)
TMP86C845UG
R/W
R/W