TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 395

• Manufacturer Part Number: TMPM361F10FG
• Manufacturer: Toshiba

Specifications of TMPM361F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Contact Us
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14Ã?14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 3
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

SCLK input
(<SCLKS>=0
Rising edge mode)
SCLK input
(<SCLKS>=0
Rising edge mode)
SCLK input
(<SCLKS>=0
Rising edge mode)
Transmit data
write timing
SCLK input
(<SCLKS>=1
Falling edge mode)
TXD
(INTTXx interrupt
Transmit data
write timing
SCLK input
(<SCLKS>=1
Falling edge mode)
Transmit data
write timing
SCLK input
(<SCLKS>=1
Falling edge mode)
request)
TXD
TBEMP
PERR
(Function to detect
TXD
(INTTXx interrupt
TBEMP
(INTTXx interrupt
underrun error)
request)
request)
Figure 12-13 Transmit Operation in the I/O Interface Mode (SCLK Input Mode)
<WBUF> = "1" (if double buffering is enabled and there is no data in buffer2)
<WBUF> = "1" (if double beffering is enabled and there is data in beffer2)
bit 0
bit 0
bit 0
bit 1
bit 1
<WBUF> = "0" (if double buffering is disabled)
bit 1
Page 371
bit 5
bit 5
bit 5
bit 6
bit 6
bit 6
bit 7
bit 7
bit 7
A
A
A
bit 0
bit 0
1
TMPM361F10FG
bit 1
bit 1
1