TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 135
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TMPM361F10FG
Manufacturer Part Number
TMPM361F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM361F10FG.pdf
(702 pages)
Specifications of TMPM361F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
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Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14Ã?14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
3
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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11-10
9
8
7
6-4
3-2
1
0
Bit
Note 1: <EMSTx> is effective only when <EMCGx[2:0]> is set to "100" for both rising and falling edge. The active level used
Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is pro-
EMST56[1:0]
−
INT5EN
−
EMCG4[2:0]
EMST4[1:0]
−
INT4EN
Bit Symbol
for the reset of standby can be checked by referring <EMSTx>. If interrupts are cleared with the CGICRCG register,
<EMSTx> is also cleared.
hibited.
R
R
R/W
R
R/W
R
R
R/W
Type
active level of INT5 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edge
Reads as undefined.
INT5 clear input
0: Disable
1: Enable
Read as 0,
active level setting of INT4 standby clear request. (101 to 111: setting prohibited)
000: "Low" level
001: "High" level
010: Falling edge
011: Rising edge
100: Both edge
active level of INT4 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edge
Reads as undefined.
INT4 clear input
0: Disable
1: Enable
Page 111
Function
TMPM361F10FG
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