TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 394
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TMPM361F10FG
Manufacturer Part Number
TMPM361F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM361F10FG.pdf
(702 pages)
Specifications of TMPM361F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
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Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14Ã?14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
3
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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12.16
Operation in Each Mode
(2)
SCLK Input Mode
・ If double buffering is disabled (SCxMOD2<WBUF> = "0")
・ If double buffer is enabled (SCxMOD2<WBUF> = "1")
ta is outputted from the TXD pin. When all data is output, an interrupt INTTXx is gener-
ated. The next transmit data must be written before the timing point "A" as shown in Fig-
ure 12-13.
writes data to the transmit buffer before the SCLK input becomes active or when data trans-
mission from the transmit shift register is completed. Simultaneously, the transmit buffer
empty flag SCxMOD2<TBEMP> is set to "1", and the INTTXx interrupt is generated.
ternal bit counter is started, an under-run error occurs and 8-bit dummy data (0xFF) is sent.
If the SCLK is input in the condition where data is written in the transmit buffer, 8-bit da-
Data is moved from the transmit buffer to the transmit shift register when the CPU
If the SCLK input becomes active while no data is in the transmit buffer, although the in-
Page 370
TMPM361F10FG
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