73S1217F Maxim, 73S1217F Datasheet - Page 95

• Manufacturer Part Number: 73S1217F
• Description: The Teridian 73S1217F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

TX Control/Status Register (STXCtl): 0xFE06
This register is used to control transmission of data to the smart card. Some control and some status bits
are in this register.
Rev. 1.2
STXCtl.7
STXCtl.6
STXCtl.5
STXCtl.4
STXCtl.3
STXCtl.2
STXCtl.1
STXCtl.0
Bit
MSB
I2CMODE
I2CMODE
TXUNDR
TXEMTY
BREAKD
TXFULL
LASTTX
Symbol
TX/RXB
–
–
I2C Mode – When in sync mode and this bit is set, and when the RLen count
value = max or 0, the source of the smart card data for IO pin (or SIO pin) will
be connected to the IO bit in
FIFO. See the description for the
TX FIFO is full. Additional writes may corrupt the contents of the FIFO. This
bit it will remain set as long as the TX FIFO is full. Generates a TX_Event
interrupt upon going full.
1 = TX FIFO is empty, 0 = TX FIFO is not empty. If there is data in the TX
FIFO, the circuit will transmit it to the smart card if in transmit mode. In T=1
mode, if the LASTTX bit is set and the hardware is configured to transmit the
CRC/LRC, the TXEMTY will not be set until the CRC/LRC is transmitted. In
T=0, if the LASTTX bit is set, TXEMTY will be set after the last word has
been successfully transmitted to the smart card. Generates a TXEVNT
interrupt upon going empty.
TX Underrrun – (Read only) Asserted when a transmit under-run condition
has occurred. An under-run condition is defined as an empty TX FIFO when
the last data word has been successfully transmitted to the smart card and
the LASTTX bit was not set. No special processing is performed by the
hardware if this condition occurs. Cleared when read by firmware. This bit
generates a TXERR interrupt.
Last TX Byte – Set by firmware (in both T=0 and T=1) when the last byte in
the current message has been written into the transmit FIFO. In T=1 mode,
the CRC/LRC will be appended to the message. Should be set after the last
byte has been written into the transmit FIFO. Should be cleared by firmware
before writing first byte of next message into the transmit FIFO. Used in T=0
to determine when to set TXEMTY.
1 = Transmit mode, 0 = Receive mode. Configures the hardware to be
receiving from or transmitting to the smart card. Determines which counters
should be enabled. This bit should be set to receive mode prior to switching
to another interface. Setting and resetting this bit shall initialize the CRC
logic. If LASTTX is set, this bit can be reset to RX mode and UART logic will
automatically change mode to RX when TX operation is completed
(TX_Empty =1).
Break Detected – (Read only) 1 = A break has been detected on the I/O line
indicating that the smart card detected a parity error. Cleared when read.
This bit generates a TXERR interrupt.
TXFULL
Table 85: The STXCtl Register
TXEMTY TXUNDR LASTTX
0x00
SCCtl
Function
Protocol Mode Register
(or SCECtl) register rather than the TX
TX/RXB
for more detail.
BREAKD
LSB
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