ST72264G2 STMicroelectronics, ST72264G2 Datasheet - Page 36

• Manufacturer Part Number: ST72264G2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72264G2

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

ST72260Gx, ST72262Gx, ST72264Gx
POWER SAVING MODES (Cont’d)
8.5 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see
Mapping,” on page
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’ to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes immediately.
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 15.1 "OPTION BYTES" on page 162
more details).
Figure 25. HALT Mode Timing Overview
36/172
INSTRUCTION
RUN
HALT
HALT
INTERRUPT
RESET
OR
4096 CPU CYCLE
32) or a RESET. When exiting
DELAY
Figure
Table 5, “Interrupt
26).
VECTOR
FETCH
Figure
RUN
25).
for
Figure 26. HALT Mode Flowchart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0]
ister are set during the interrupt routine and
cleared when the CC register is popped.
N
HALT INSTRUCTION
WATCHDOG
WDGHALT
Table 5, “Interrupt Mapping,” on page 32
RESET
1
INTERRUPT
Y
1)
3)
ENABLE
4096 CPU CLOCK CYCLE
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
DELAY
bits
RESET
Y
WATCHDOG
in the CC reg-
DISABLE
2)
XX
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
0
1
4)
for