ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 99

• Manufacturer Part Number: ST72361AR9-Auto
• Description: 8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
• Manufacturer: STMicroelectronics

Specifications of ST72361AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72361xx-Auto
Input Capture control / status register (ARTICCSR)
Note: When an OPx bit is modified, the PWMx output signal polarity is immediately
PWM control register (PWMCR)
Read/write
Reset value: 0000 0000 (00h)
Bit 7:4 = OE[3:0] PWM Output Enable
These bits are set and cleared by software. They enable or disable the PWM output
channels independently acting on the corresponding I/O pin.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They independently select the polarity of the
four PWM output signals.
Table 45.
Duty cycle registers (PWMDCRx)
Read/write
Reset value: 0000 0000 (00h)
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx register of each PWM channel to
determine the second edge location of the PWM signal (the first edge location is common to
all channels and given by the ARTARR register). These PWMDCR registers allow the duty
cycle to be set independently for each PWM channel.
Read/Write
Reset value: 0000 0000 (00h)
OE3
DC7
0: PWM output disabled.
1: PWM output enabled.
7
7
reversed.
Counter <= OCRx
PWMx output level and polarity
OE2
DC6
1
0
OE1
DC5
PWMx output level
Doc ID 12468 Rev 3
OE0
DC4
Counter > OCRx
OP3
DC3
0
1
PWM auto-reload timer (ART)
OP2
DC2
OP1
DC1
OPx
0
1
OP0
DC0
0
0
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