ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 50

• Manufacturer Part Number: ST72361AR9-Auto
• Description: 8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
• Manufacturer: STMicroelectronics

Specifications of ST72361AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

Interrupts
Note:
Caution:
Caution:
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When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
RESET, TRAP and TLI can be considered as having the highest software priority in the
decision process.
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (RESET, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit HALT mode.
●
This software interrupt is serviced when the TRAP instruction is executed. It will be serviced
according to the flowchart in
TRAP can be interrupted by a TLI.
●
The RESET source has the highest priority in the ST7. This means that the first current
routine has the highest software priority (level 3) and the highest hardware priority.
See the RESET chapter for more details.
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
●
This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin.
A TRAP instruction must not be used in a TLI service routine.
●
External interrupts allow the processor to exit from HALT low power mode.
External interrupt sensitivity is software selectable through the External Interrupt Control
register (EICR).
External interrupt triggered on edge will be latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.
●
Usually the peripheral interrupts cause the MCU to exit from HALT mode except those
mentioned in the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and
TRAP (Non Maskable Software Interrupt)
RESET
TLI (Top Level Hardware Interrupt)
External Interrupts
Peripheral Interrupts
Figure
17). After stacking the PC, X, A and CC registers (except for RESET), the
Figure 17
Doc ID 12468 Rev 3
as a TLI.
ST72361xx-Auto