ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 139

• Manufacturer Part Number: ST72361AR9-Auto
• Description: 8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
• Manufacturer: STMicroelectronics

Specifications of ST72361AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72361xx-Auto
13.7.3
Bit 4 = PWM Pulse Width Modulation.
Bit 3, 2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 55.
1.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition on the ICAP2 pin will trigger the capture.
Bit 0 = Reserved, must be kept at 0.
Control/status register (CSR)
Read only (except bit 2 R/W)
Reset value: 0000 0000 (00h)
Bit 7 = ICF1 Input Capture Flag 1.
Bit 6 = OCF1 Output Compare Flag 1.
Bit 5 = TOF Timer Overflow Flag.
Not available in Slow mode in ST72F361.
ICF1
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
length of the pulse depends on the value of OC1R register; the period depends on the
value of OC2R register.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0: no input capture (reset value).
1: an input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the IC1R register.
0: no match (reset value).
1: the content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the OC1R
register.
0: no timer overflow (reset value).
1: the free running counter rolled over from FFh to 00h. To clear this bit, first read the
SR register, then read or write the CTR register.
7
Clock control bits
f
OSC2
Timer clock
OCF1
f
f
f
CPU
CPU
CPU
/ 8000
/ 4
/ 2
/ 8
(1)
TOF
Doc ID 12468 Rev 3
ICF2
CC1
0
0
1
1
OCF2
TIMD
8-bit timer (TIM8)
CC0
0
0
1
0
1
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0
0