ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 87

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
9.8
9.9
9.10
9.10.1
9.10.2
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
Using halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled.
●
Interrupts
None.
Register description
Control register (WDGCR)
Read/Write
Reset value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog counter. It is decremented every 16384 f
cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes
cleared).
Window Register (WDGWR)
Read/ write
Reset value: 0111 1111 (7Fh)
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
These bits contain the window value to be compared to the downcounter.
WDGA
Before executing the HALT instruction, refresh the WDG counter, to avoid an
unexpected WDG reset immediately after waking up the microcontroller.
0: Watchdog disabled
1: Watchdog enabled
7
7
-
W6
T6
W5
T5
Doc ID 12370 Rev 8
W4
T4
W3
T3
Window watchdog (WWDG)
W2
T2
W1
T1
W0
T0
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0
OSC2
0