ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 205
ST72561J6-Auto
Manufacturer Part Number
ST72561J6-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet
1.ST72561R9-AUTO.pdf
(324 pages)
Specifications of ST72561J6-Auto
Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
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ST72561-Auto
16.5
16.6
16.7
Low power modes
Table 73.
Interrupts
Table 74.
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding enable control bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
SCI synchronous transmission
The SCI transmitter allows the user to control a one way synchronous serial transmission.
The SCLK pin is the output of the SCI transmitter clock. No clock pulses are sent to the
SCLK pin during start bit and stop bit. Depending on the state of the LBCL bit in the SCICR3
register, clock pulses are or are not be generated during the last valid data bit (address
mark). The CPOL bit in the SCICR3 register allows the user to select the clock polarity, and
the CPHA bit in the SCICR3 register allows the user to select the phase of the external clock
(see
During idle, preamble and send break, the external SCLK clock is not activated.
These options allow the user to serially control peripherals which consist of shift registers,
without losing any functions of the SCI transmitter which can still talk to other SCI receivers.
These options do not affect the SCI receiver which is independent from the transmitter.
WAIT
HALT
Transmit data register empty
Transmission complete
Received data ready to be read
Overrun error detected
Idle line detected
Parity error
Figure
Mode
91,
Interrupt event
Effect of low power modes on SCI
SCI interrupt control and wake-up capability
Figure 92
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
In halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
and
Doc ID 12370 Rev 8
Figure
LINSCI serial communication interface (LIN master only)
93).
TDRE
TC
RDRF
OR
IDLE
PE
Event
flag
Description
TIE
TCIE
RIE
ILIE
PIE
control
Enable
bit
Yes
from
wait
Exit
No
from
Exit
halt
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