ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 168

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

LINSCI serial communication interface (LIN master/slave)
15.6
15.7
168/324
Example 2: data = 00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS
bit = 0).
Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the character made of the
7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example 3: data = 00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit
= 1).
Transmission mode
If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted
but is changed by the parity bit.
Reception mode
If the PCE bit is set then the interface checks if the received data byte has an even number
of “1s” if even parity is selected (PS = 0) or an odd number of “1s” if odd parity is selected
(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is
generated if PCIE is set in the SCICR1 register.
Low power modes
Table 61.
Interrupts
Table 62.
WAIT
HALT
Transmit Data Register Empty
Transmission Complete
Received Data Ready to be Read
Overrun Error or LIN Synch Error
Detected
Idle Line Detected
Parity Error
LIN Header Detection
Mode
Interrupt event
Effect of low power modes on SCI
SCI interrupt control and wake-up capability
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Doc ID 12370 Rev 8
OR/LHE
RDRF
Event
TDRE
LHDF
IDLE
flag
TC
PE
Description
control
Enable
TCIE
LHIE
ILIE
RIE
TIE
PIE
bit
from
Wait
Exit
Yes
ST72561-Auto
from
Halt
Exit
No