ST72262G1 STMicroelectronics, ST72262G1 Datasheet - Page 67

• Manufacturer Part Number: ST72262G1
• Description: 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72262G1

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

16-BIT TIMER (Cont’d)
3. In PWM mode the ICAP1 pin can not be used
11.3.4 Low Power Modes
11.3.5 Interrupts
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
11.3.6 Summary of Timer modes
1)
2)
3)
WAIT
HALT
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
PWM Mode
See note 4 in
See note 5 in
See note 4 in
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
Mode
MODES
No effect on 16-bit Timer.
Timer interrupts cause the Device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the Device is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the Device is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the Device is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
Section 11.3.3.5 "One Pulse Mode" on page 64
Section 11.3.3.5 "One Pulse Mode" on page 64
Section 11.3.3.6 "Pulse Width Modulation Mode" on page 66
Interrupt Event
Input Capture 1
Yes
Yes
No
No
Not Recommended
Not Recommended
Input Capture 2
Description
4. When the Pulse Width Modulation (PWM) and
AVAILABLE RESOURCES
Yes
Yes
ICF1 can also generates interrupt if ICIE is set.
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
ST72260Gx, ST72262Gx, ST72264Gx
1)
3)
Output Compare 1 Output Compare 2
Event
OCF1
OCF2
ICF1
ICF2
Flag
TOF
Yes
Yes
No
No
Control
Enable
OCIE
TOIE
ICIE
Bit
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Partially
Yes
Yes
No
from
Halt
Exit
67/172
No
No
No
No
No
2)