ST72262G1 STMicroelectronics, ST72262G1 Datasheet - Page 45

• Manufacturer Part Number: ST72262G1
• Description: 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72262G1

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
10.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows you to have
two fully independent external interrupt source
sensitivities with configurable sources (using the
EXTIT option bit) as shown in
ure
Each external interrupt source can be generated
on four different events on the pin:
■
■
■
■
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I[1:0] bits in the CC register are set to 1
(interrupt masked). See
REGISTER DESCRIPTION" on page 43
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page 46
programming.
10.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
■
■
These functions are described in detail in the
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page
– SS pin internal control to use the PB7 I/O port
– Master output capability on the MOSI pin
– Slave output capability on the MISO pin (PB5)
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Main clock signal (f
SPI pin configuration:
30.
function while the SPI is active.
(PB4) deactivated while the SPI is active.
deactivated while the SPI is active.
CPU
46.
) output on PC2
Section 9.8 "I/O PORT
for more details on the
Figure 29
and
and
Sec-
Sec-
Fig-
Figure 29. Ext. Interrupt Sensitivity (EXTIT=0)
Figure 30. Ext. Interrupt Sensitivity (EXTIT=1)
PC5
PC0
PA7
PA0
PB7
PB0
PC5
PC0
PA7
PA0
PB7
PB0
ST72260Gx, ST72262Gx, ST72264Gx
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
SOURCE
SOURCE
SOURCE
SOURCE
ei0
ei1
ei0
ei1
SENSITIVITY
SENSITIVITY
IS00
IS10
SENSITIVITY
SENSITIVITY
IS00
IS10
CONTROL
CONTROL
CONTROL
CONTROL
MISCR1
MISCR1
MISCR1
MISCR1
IS01
IS11
IS01
IS11
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