ST7232AJ2 STMicroelectronics, ST7232AJ2 Datasheet - Page 55

• Manufacturer Part Number: ST7232AJ2
• Description: 8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST7232AJ2

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Table 15. Main Clock Controller Register Map and Reset Values
Address
002Dh
(Hex.)
002Ch
MCCSR
Reset Value
MCCBCR
Reset Value
Register
Label
MCO
7
0
0
CP1
6
0
0
CP0
5
0
0
MCC BEEP CONTROL REGISTER (MCCBCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
BC1
7
0
SMS
0
0
1
1
4
0
0
0
BC0
0
1
0
1
TB1
3
0
0
0
Beep mode with f
0
~500-Hz
~1-KHz
~2-KHz
TB0
2
0
0
0
Off
BC1
OIE
0
~50% duty cycle
1
0
0
OSC2
Beep signal
BC1
Output
ST7232A
=8MHz
BC0
OIF
55/157
0
0
0
BC0
0
1