ST7232AJ2 STMicroelectronics, ST7232AJ2 Datasheet - Page 132

• Manufacturer Part Number: ST7232AJ2
• Description: 8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST7232AJ2

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232A
CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 74. RESET pin protection
1. The reset network protects the device against parasitic resets.
2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (watchdog).
3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
132/157
1
Required
EXTERNAL
CIRCUIT
RESET
IL
USER
Recommended for EMC
max. level specified in
INJ(RESET)
V
DD
0.01µF
0.01µF
in
Section 12.2.2 on page
Section 12.9.1
1)2)3)4)
V
DD
4.7kΩ
. Otherwise the reset will not be taken into account internally.
114.
V
DD
R
ON
Filter
GENERATOR
PULSE
INTERNAL
RESET
WATCHDOG
ST72XXX