ST7232AJ2 STMicroelectronics, ST7232AJ2 Datasheet - Page 155

• Manufacturer Part Number: ST7232AJ2
• Description: 8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST7232AJ2

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
15.2 ROM DEVICES ONLY
15.2.1 I/O Port A and F Configuration
When using an external quartz crystal or ceramic
resonator, a few f
when the signal pattern in
because this pattern causes the device to enter
test mode and return to user mode after a few
clock periods. User program execution and I/O
status are not changed, only a few clock cycles are
lost.
This happens with either one of the following con-
figurations:
PA3=0, PF4=1, PF1=0 while PLL option is disa-
bled and PF0 is toggling
PA3=0, PF4=1, PF1=0, PF0=1 while PLL option is
enabled
This is detailed in the following table
Table 31. Port A and F Configuration:
PLL PA3 PF4 PF1
OFF
ON
0
0
1
1
OSC2
0
0
Toggling
clock periods may be lost
PF0
Table 31
1
Max. 2 clock cy-
cles lost at each
rising or falling
edge of PF0
Max. 1 clock cy-
cle lost out of
every 16
Disturbance
occurs . This is
Clock
15.1.6 39-Pulse ICC Entry Mode
For Flash devices, ICC mode entry using ST7 ap-
plication clock (39 pulses) is not supported. Exter-
nal clock mode must be used (36 pulses). Refer to
the ST7 Flash Programming Reference Manual.
As a consequence, for cycle-accurate operations,
these configurations are prohibited in either input
or output mode.
Workaround:
To avoid this occurring, it is recommended to con-
nect one of these pins to GND (PF4 or PF0) or
V
15.2.2 External clock source with PLL
PLL is not supported with external clock source.
DD
(PA3 or PF1).
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