ST7LITE25F2 STMicroelectronics, ST7LITE25F2 Datasheet - Page 77

• Manufacturer Part Number: ST7LITE25F2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LITE25F2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.6 Low Power Modes
11.4.6.1 Using the SPI to wake-up the Device
from Halt mode
In slave configuration, the SPI is able to wake-up
the
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake-up the
Halt mode only if the Slave Select signal (external
WAIT
HALT
Mode
Device
from HALT mode through a SPIF inter-
No effect on SPI.
SPI interrupt events cause the Device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the Device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
Description
Device
from
SS pin or the SSI bit in the SPICSR register) is low
when the
lection is configured as external (see
11.4.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
11.4.7 Interrupts
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
SPI End of Trans-
fer Event
Master Mode
Fault Event
Overrun Error
Interrupt Event
Device
enters Halt mode. So if Slave se-
MODF
Event
SPIF
OVR
Flag
Control
Enable
SPIE
Bit
from
Wait
Exit
Yes
Yes
Yes
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Section
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from
Exit
Halt
Yes
No
No
1