ST7LITE25F2 STMicroelectronics, ST7LITE25F2 Datasheet - Page 53

• Manufacturer Part Number: ST7LITE25F2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LITE25F2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: it counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see
.Watchdog
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
– The T[5:0] bits contain the number of increments
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Table 12.Watchdog Timing
diate reset
which represents the time delay before the
watchdog produces a reset.
Counter
Code
WDG
C0h
FFh
Timing):
f
CPU
[ms]
= 8MHz
min
127
1
[ms]
max
128
Table 12
2
Notes:
1. The timing variation shown in
the unknown status of the prescaler when writing
to the CR register.
2. The number of CPU clock cycles applied during
the RESET phase (256 or 4096) must be taken
into account in addition to these timings.
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
Refer to the Option Byte description in
on page
11.1.4.1 Using Halt Mode with the WDG
(WDGHALT option)
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller. Same behavior in active-halt
mode.
122.
Table 12
ST7LITE2
section 15
is due to
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