ST7LITE25F2 STMicroelectronics, ST7LITE25F2 Datasheet - Page 70

• Manufacturer Part Number: ST7LITE25F2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LITE25F2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7LITE2
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
11.4.2 Main Features
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■
■
■
■
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Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
Figure 42. Serial Peripheral Interface Block Diagram
70/133
1
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
MOSI
MISO
CPU
SCK
SS
/2 max. slave mode frequency (see note)
SOD
bit
SPIDR
8-Bit Shift Register
Read Buffer
SERIAL CLOCK
CPU
GENERATOR
CONTROL
MASTER
/4 max.)
Data/Address Bus
Read
Write
11.4.3 General Description
Figure 42
(SPI) block diagram. There are 3 registers:
The SPI is connected to external devices through
3 pins:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
– SS: Slave select:
put by SPI slaves
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master
7
SPIE
SPIF WCOL
7
SPE
shows the serial peripheral interface
CONTROL
SPR2
OVR
STATE
SPI
Interrupt
request
MODF
MSTR
CPOL
0
CPHA
SOD
Device
SS
SPICR
SPICSR
SSM
SPR1
.
0
1
SPR0
SSI
0
0