ST72324J2 STMicroelectronics, ST72324J2 Datasheet - Page 16

• Manufacturer Part Number: ST72324J2
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J2

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324Jx ST72324Kx
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
2. The bits associated with unavailable pins must always keep their reset value.
3. The Timer A Input Capture 2 pin is not available (not bonded).
4. The Timer A Output Compare 2 pin is not available (not bonded).
Caution: The TAIC2HR and TAIC2LR registers and the ICF2 and OCF2 flags are not present in Flash de-
vices but are present in the emulator. For compatibility with the emulator, it is recommended to perform a
dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.
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– In Flash devices:
– The TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values.
tion, the values of the I/O pins are returned instead of the DR register contents.
The TAIC2HR and TAIC2LR registers are not present. Bit 5 of the TACSR register (ICF2) is forced
by hardware to 0. Consequently, the corresponding interrupt cannot be used.
Bit 4 of the TACSR register (OCF2) is forced by hardware to 0. Consequently, the corresponding in-
terrupt cannot be used.