ST72324J2 STMicroelectronics, ST72324J2 Datasheet - Page 103

• Manufacturer Part Number: ST72324J2
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J2

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
SCP1
DR7
7
7
PR Prescaling factor
SCP0
DR6
Figure
Figure
13
SCT2
1
3
4
DR5
1.).
1.).
SCT1
DR4
SCT0
DR3
SCP1
SCR2 SCR1 SCR0
DR2
0
0
1
1
DR1
SCP0
0
1
0
1
DR0
0
0
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR Dividing factor
TR dividing factor
128
128
16
32
64
16
32
64
1
2
4
8
1
2
4
8
ST72324Jx ST72324Kx
SCR2
SCT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SCR1
SCT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SCR0
103/164
SCT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1