ST72324J2 STMicroelectronics, ST72324J2 Datasheet - Page 150

• Manufacturer Part Number: ST72324J2
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J2

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324Jx ST72324Kx
14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION
14.1 FLASH OPTION BYTES
The option bytes allows the hardware configura-
tion of the microcontroller to be selected. They
have no address in the memory map and can be
accessed only in programming mode (for example
using a standard ST7 programming tool). The de-
fault content of the FLASH is fixed to FFh. To pro-
gram directly the FLASH devices using ICP,
FLASH devices are shipped to customers with the
internal RC clock source.
OPTION BYTE 0
OPT7= WDG HALT Watchdog reset on HALT
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = Reserved, must be kept at default value.
OPT4:3= VD[1:0] Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD.
150/164
1
Default
7
1
WDG
1
STATIC OPTION BYTE 0
1
1
0
VD
0
0
1
1
1
0
Caution: If the medium or low thresholds are se-
lected, the detection may occur outside the speci-
fied operating voltage range. Below 3.8V, device
operation is not guaranteed. For details on the
AVD and LVD threshold levels refer to
12.4.1 on page 119
OPT2:1 = Reserved, must be kept at default value.
OPT0= FMP_R Flash memory read-out protection
Read-out protection, when selected, provides a
protection against Program Memory content ex-
traction and against write access to Flash memo-
ry.
Erasing the option bytes when the FMP_R option
is selected causes the whole user memory to be
erased first, and the device can be reprogrammed.
Refer to Section 7.3.1 on page 37 and the ST7
Flash Programming Reference Manual for more
details.
0: Read-out protection enabled
1: Read-out protection disabled
Lowest Voltage Threshold (V
Medium Voltage Threshold (V
Highest Voltage Threshold (V
1
7
Selected Low Voltage Detector
1
LVD and AVD Off
STATIC OPTION BYTE 1
OSCTYPE
1
1
0
0
DD
DD
DD
2
1
~3V)
OSCRANGE
~4V)
~3.5V)
1
1
VD1
1
1
0
0
0
1
Section
VD0
0
1
0
1
0
1