ST72561R9-Auto STMicroelectronics, ST72561R9-Auto Datasheet - Page 94

• Manufacturer Part Number: ST72561R9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561R9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

PWM auto-reload timer (ART)
11.2
11.2.1
11.2.2
11.2.3
11.2.4
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Functional description
Counter
The free running 8-bit counter is fed by the output of the prescaler, and is incremented on
every rising edge of the clock signal.
It is possible to read or write the contents of the counter on the fly by reading or writing the
Counter Access register (ARTCAR).
When a counter overflow occurs, the counter is automatically reloaded with the contents of
the ARTARR register (the prescaler is not affected).
Counter clock and prescaler
The counter clock frequency is given by:
f
The timer counter’s input clock (f
selects one of the eight available taps of the prescaler, as defined by CC[2:0] bits in the
Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2
(where n = 0, 1...7).
This f
can be either the f
The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the
ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter
contents are frozen. When TCE is set, the counter runs at the rate of the selected clock
source.
Counter and prescaler Initialization
After RESET, the counter and the prescaler are cleared and f
The counter can be initialized by:
●
●
In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known
value.
Direct access to the prescaler is not possible.
Output compare control
The timer compare function is based on four different comparisons with the counter (one for
each PWMx output). Each comparison is made between the counter value and an output
compare register (OCRx) value. This OCRx register can not be accessed directly, it is
loaded from the duty cycle register (PWMDCRx) at each overflow of the counter.
This double buffering method avoids glitch generation when changing the duty cycle on the
fly.
COUNTER
Writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load)
and the TCE (Timer Counter Enable) bits in the ARTCSR register.
Writing to the ARTCAR counter access register,
INPUT
= f
frequency source is selected through the EXCL bit of the ARTCSR register and
INPUT
CPU
/ 2
CC[2:0]
or an external input frequency f
Doc ID 12370 Rev 8
INPUT
) feeds the 7-bit programmable prescaler, which
EXT
.
INPUT
= f
CPU
.
ST72561-Auto
n