ST72561R9-Auto STMicroelectronics, ST72561R9-Auto Datasheet - Page 53

• Manufacturer Part Number: ST72561R9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561R9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
6.3
Note:
6.4
if the corresponding enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status register
followed by a read or write to an associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being serviced) will therefore be lost if the clear sequence is executed.
Interrupts and low power modes
All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the HALT modes (see
column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are
present while exiting HALT mode, the first one serviced can only be an interrupt with exit
from HALT mode capability and it is selected through the same decision process shown in
Figure
If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced after the first one serviced.
Concurrent & nested management
The following
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in
lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for
each interrupt.
Figure 19. Concurrent interrupt management
Warning:
18.
Figure 19
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MAIN
RIM
Figure
A stack overflow may occur without notifying the software of
the failure.
20. The interrupt hardware priority is given in this order from the
and
IT2
Figure 20
IT1
Doc ID 12370 Rev 8
TLI
show two different interrupt management modes. The
IT1
IT0
IT3
IT4
10
SOFTWARE
PRIORITY
LEVEL
MAIN
3
3
3
3
3
3
3/0
I1
1 1
1 1
1 1
1 1
1 1
1 1
Interrupts
I0
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