STM8L162M8 STMicroelectronics, STM8L162M8 Datasheet - Page 83
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STM8L162M8
Manufacturer Part Number
STM8L162M8
Description
STM8L-Ultra Low Power-8 bits Microcontrollers
Manufacturer
STMicroelectronics
Datasheet
1.STM8L162R8.pdf
(121 pages)
Specifications of STM8L162M8
Operating Power Supply
1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR)
Temperature Range
− 40 to 85 or 125 °C
5 Low Power Modes
Wait, Low power run, Low power wait, Active-halt with RTC, Halt
Ultralow Leakage Per I/0
50 nA
Fast Wakeup From Halt
5 μs
Max Freq
16 MHz, 16 CISC MIPS peak
Lcd
8x40 or 4x44 w/ step-up converter
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8L162M8T6
Manufacturer:
STMicroelectronics
Quantity:
200
Company:
Part Number:
STM8L162M8T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM8L162R8, STM8L162M8
3. Data based on a differential I
4. Data based on a differential I
5. Peripherals listed above the I
6. Data based on a differential I
7. Data based on a differential I
8. Data based on a differential I
9. Including supply current of internal reference voltage.
Table 27.
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
9.3.4
Symbol
I
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins
toggling. Not tested in production.
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins
toggling. Not tested in production.
V
enabled with static inputs. Supply current of internal reference voltage excluded.
PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.
DD(RST)
DD
/2. Floating DAC output.
Current consumption under external reset
Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for V
Table 28.
1. Guaranteed by design, not tested in production.
C
f
I
Supply current under
external reset
HSE_ext
LEAK_HSE
Symbol
in(HSE)
V
V
HSEH
HSEL
(1)
(1)
Parameter
External clock source
frequency
OSC_IN input pin high level
voltage
OSC_IN input pin low level
voltage
OSC_IN input capacitance
OSC_IN input leakage
current
HSE external clock characteristics
DD
DD
DD
DD
DD
DD(ALL)
(1)
measurement between the on-chip peripheral in reset configuration and not clocked and
measurement between the on-chip peripheral in reset configuration and not clocked and
measurement between ADC in reset configuration and continuous ADC conversion.
measurement between DAC in reset configuration and continuous DAC conversion of
measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2
Parameter
parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.
PB1/PB3/PA5 pins are
externally tied to V
Doc ID 17959 Rev 2
V
SS
Conditions
< V
Conditions
DD
DD
IN
< V
and T
DD
A
V
V
.
V
0.7 x V
DD
DD
DD
Min.
V
= 1.8 V
= 3.6 V
1
SS
= 3 V
DD
Typ.
2.6
Electrical parameters
Typ.
48
80
95
0.3 x V
Max.
V
±1
16
DD
DD
Unit
µA
83/121
MHz
Unit
pF
µA
V