STM8L162M8 STMicroelectronics, STM8L162M8 Datasheet - Page 57
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STM8L162M8
Manufacturer Part Number
STM8L162M8
Description
STM8L-Ultra Low Power-8 bits Microcontrollers
Manufacturer
STMicroelectronics
Datasheet
1.STM8L162R8.pdf
(121 pages)
Specifications of STM8L162M8
Operating Power Supply
1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR)
Temperature Range
− 40 to 85 or 125 °C
5 Low Power Modes
Wait, Low power run, Low power wait, Active-halt with RTC, Halt
Ultralow Leakage Per I/0
50 nA
Fast Wakeup From Halt
5 μs
Max Freq
16 MHz, 16 CISC MIPS peak
Lcd
8x40 or 4x44 w/ step-up converter
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8L162M8T6
Manufacturer:
STMicroelectronics
Quantity:
200
Company:
Part Number:
STM8L162M8T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM8L162R8, STM8L162M8
7
Table 11.
Address
00 480C
00 480A
00 480B
00 4800
00 4802
00 4807
00 4808
00 4809
Boot code size)
clock cycles for
Brownout reset
Option name
HSE and LSE
PCODESIZE
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.
All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See
The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP, UBC and PCODESIZE values which can only be taken into account when they are
modified in ICP mode (with the SWIM).
Refer to the STM8L15x/STM8L16x Flash programming manual (PM0054) and STM8 SWIM
and Debug Manual (UM0320) for information on SWIM programming procedures.
Option byte addresses
Independent
option bytes
stabilization
Bootloader
Number of
UBC (User
oscillators
protection
watchdog
Read-out
(OPTBL)
(ROP)
(BOR)
option
Table 11
OPTBL
Option
OPT0
OPT1
OPT2
OPT3
OPT4
OPT5
[15:0]
byte
[3:0]
[3:0]
No.
for details on option byte addresses.
7
Doc ID 17959 Rev 2
Reserved
Reserved
Reserved
6
5
4
OPTBL[15:0]
PCODE[7:0]
Option bits
ROP[7:0]
UBC[7:0]
WWDG
_HALT
LSECNT[1:0]
3
BOR_TH
WWDG
_HW
2
_HALT
IWDG
HSECNT[1:0]
1
IWDG
BOR_
_HW
ON
Option bytes
0
Factory
default
setting
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
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