STM32W108HB STMicroelectronics, STM32W108HB Datasheet - Page 94

• Manufacturer Part Number: STM32W108HB
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108HB

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

Serial interfaces
Note:
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DMA memory buffer terminology:
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To use a DMA channel, software should follow these steps:
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A DMA buffer's end address, SCx_TXENDA/B (or SCx_RXENDA/B), can be written while
the buffer is loaded or active. This is useful for receiving messages that contain an initial
byte count, since it allows software to set the buffer end address at the last byte of the
message.
As the DMA channel transfers data between the transmit or receive FIFO and a memory
buffer, the DMA count register contains the byte offset from the start of the buffer to the
address of the next byte that will be written or read. A transmit DMA channel has a single
DMA count register (SCx_TXCNT) that applies to whichever transmit buffer is active, but a
receive DMA channel has two DMA count registers (SCx_RXCNTA/B), one for each receive
buffer. The DMA count register contents are preserved until the corresponding buffer, or
either buffer in the case of the transmit DMA count, is loaded, or until the DMA is reset.
The receive DMA count register may be written while the corresponding buffer is loaded. If
the buffer is not loaded, writing the DMA count register also loads the buffer while
preserving the count value written. This feature can simplify handling UART receive errors.
The DMA channel stops using a buffer and unloads it when the following is true:
Typically a transmit buffer is unloaded after all its data has been sent, and a receive buffer is
unloaded after it is filled with data, but writing to the buffer end address or buffer count
registers can also cause a buffer to unload early.
Serial controller DMA channels include additional features specific to the SPI and UART
operation and are described in those sections.
load - make a buffer available for the DMA channel to use
pending - a buffer loaded but not yet active
active - the buffer that will be used for the next DMA transfer
unload - DMA channel action when it has finished with a buffer
idle - a buffer that has not been loaded, or has been unloaded
Reset the DMA channel by setting the SC_TXDMARST (or SC_RXDMARST) bit in the
SCx_DMACTRL register.
Set up the DMA buffers. The two DMA buffers, A and B, are defined by writing the start
address to SCx_TXBEGA/B (or SCx_RXBEGA/B) and the (inclusive) end address to
SCx_TXENDA/B (or SCx_RXENDA/B). Note that DMA buffers must be in RAM.
Configure and initialize SCx for the desired operating mode.
Enable second level interrupts triggered when DMA buffers unload by setting the
INT_SCTXULDA/B (or INT_SCRXULDA/B) bits in the INT_SCxFLAG register.
Enable top level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET
register.
Start the DMA by loading the DMA buffers by setting the SC_TXLODA/B (or
SC_RXLODA/B) bits in the SCx_DMACTRL register.
(DMA buffer start address + DMA buffer count) > DMA buffer end address
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Doc ID 16252 Rev 13