STM32F417IE STMicroelectronics, STM32F417IE Datasheet - Page 129

• Manufacturer Part Number: STM32F417IE
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 512 Kbytes Flash, 168 MHz CPU, Art Accelerator, Ethernet, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F417IE

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Cryptographic Acceleration: hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
• Rtc: subsecond accuracy, hardware calendar

STM32F415xx, STM32F417xx
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 72.
1. C
2. Based on characterization, not tested in production.
t
t
h(Data_NWE)
t
t
t
t
v(NADV_NE)
h(NE_NWE)
t
v(NWE_NE)
h(BL_NWE)
v(Data_NE)
t
Symbol
h(A_NWE)
t
t
t
v(BL_NE)
L
w(NADV)
w(NWE)
v(A_NE)
t
= 30 pF.
w(NE)
FSMC_NBL[1:0]
FSMC_NADV
FSMC_A[25:0]
FSMC_D[15:0]
FSMC_NWE
FSMC_NOE
FSMC_NEx
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
Data to FSMC_NEx low to Data valid
Data hold time after FSMC_NWE high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
(1)
Doc ID 022063 Rev 2
t
t
v(NADV_NE)
v(NWE_NE)
t
v(A_NE)
t
t
t
v(BL_NE)
w(NADV)
v(Data_NE)
Parameter
Address
t
w(NE)
NBL
t
w(NWE)
t
h(Data_NWE)
t
h(BL_NWE)
t
h(A_NWE)
Data
T
T
T
T
T
T
HCLK
3T
HCLK
HCLK
Electrical characteristics
HCLK
HCLK
HCLK
Min
HCLK
-
-
-
-
-
–0.5
– 2
– 1
–1
–1
–1
t
h(NE_NWE)
3T
T
T
T
T
HCLK
HCLK
HCLK
HCLK
HCLK
Max
1.5
0
2
-
-
-
-
+0.5
+0.5
ai14990
+2
+3
+ 4
(1)(2)
129/168
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns