LPC2939 NXP Semiconductors, LPC2939 Datasheet - Page 55

• Manufacturer Part Number: LPC2939
• Description: The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocksoperating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
2.
LPC2939_3
Product data sheet
Generation of the main clock is restricted by the frequency range of the PLL clock input. See
6.16.2.2 PLL functional description
generator. The RDET register keeps track of which clocks are active and inactive, and the
appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock
detector can also generate interrupts at clock activation and deactivation so that the
system can be notified of a change in internal clock status.
Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no
positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock
is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be
detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After
reset all clocks are assumed to be ‘non-present’, so the RDET status register will be
correct only after 32 BASE_PCR_CLK cycles.
Note that this mechanism cannot protect against a currently-selected clock going from
active to inactive state. Therefore an inactive clock may still be sent to the system under
special circumstances, although an interrupt can still be generated to notify the system.
Glitch-Free Switching:
switched glitch-free, both at the output generator stage and also at secondary source
generators.
In the case of the PLL the clock will be stopped and held LOW for long enough to allow
the PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the
switch will occur as quickly as possible, although there will always be a period when the
clock is held LOW due to synchronization requirements.
If the current clock is HIGH and does not go LOW within 32 cycles of BASE_PCR_CLK it
is assumed to be inactive and is asynchronously forced LOW. This prevents deadlocks on
the interface.
A block diagram of the PLL is shown in
analog section. This block compares the phase and frequency of the inputs and generates
the main clock
divider to create the output clock, or sent directly to the output. The main output clock is
then divided by M by the programmable feedback divider to generate the feedback clock.
The output signal of the analog section is also monitored by the lock detector to signal
when the PLL has locked onto the input clock.
2
. These clocks are either divided by 2  P by the programmable post
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 7 April 2010
Provisions are included in the CGU to allow clocks to be
ARM9 microcontroller with CAN, LIN, and USB
Figure
14. The input clock is fed directly to the
Table
36, Dynamic characteristics.
LPC2939
© NXP B.V. 2010. All rights reserved.
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