LPC2292_2294 NXP Semiconductors, LPC2292_2294 Datasheet - Page 13

• Manufacturer Part Number: LPC2292_2294
• Description: The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU withreal-time emulation and embedded trace support, together with 256 kB of embeddedhigh-speed flash memory
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 4.
LPC2292_2294
Product data sheet
Symbol
P3[17]/A17
P3[18]/A18
P3[19]/A19
P3[20]/A20
P3[21]/A21
P3[22]/A22
P3[23]/A23/
XCLK
P3[24]/CS3
P3[25]/CS2
P3[26]/CS1
P3[27]/WE
P3[28]/BLS3/
AIN7
P3[29]/BLS2/
AIN6
P3[30]/BLS1
P3[31]/BLS0
TD1
RESET
XTAL1
XTAL2
V
V
V
V
SS
SSA
SSA(PLL)
DD(1V8)
Pin description
Pin (LQFP)
48
47
46
45
44
41
40
36
35
30
29
28
27
97
96
22
135
142
141
3, 9, 26, 38,
54, 67, 79,
93, 103, 107,
111, 128
139
138
37, 110
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…continued
Pin
(TFBGA)
N5
M5
L5
K5
N4
K4
N3
M2
M1
K2
K1
J4
J3
E13
F10
H2
C5
C3
B3
C2, E4, J2,
N2, N7, L10,
K12, F13,
D11, B13,
B11, D7
C4
B4
N1, A12
[6]
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[9]
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All information provided in this document is subject to legal disclaimers.
[1]
Type
O
O
O
O
O
O
I/O
O
O
O
O
O
O
I
O
I
O
O
O
I
I
O
I
I
I
I
16/32-bit ARM microcontrollers with external memory interface
Rev. 8 — 8 June 2011
Description
A17 — External memory address line 17.
A18 — External memory address line 18.
A19 — External memory address line 19.
A20 — External memory address line 20.
A21 — External memory address line 21.
A22 — External memory address line 22.
A23 — External memory address line 23.
XCLK — Clock output.
CS3 — LOW-active Chip Select 3 signal.
(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)
CS2 — LOW-active Chip Select 2 signal.
(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)
CS1 — LOW-active Chip Select 1 signal.
(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)
WE — LOW-active Write enable signal.
BLS3 — LOW-active Byte Lane Select signal (Bank 3).
AIN7 — ADC, input 7. This analog input is always connected
to its pin.
BLS2 — LOW-active Byte Lane Select signal (Bank 2).
AIN6 — ADC, input 6. This analog input is always connected
to its pin.
BLS1 — LOW-active Byte Lane Select signal (Bank 1).
BLS0 — LOW-active Byte Lane Select signal (Bank 0).
TD1: CAN1 transmitter output.
External Reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator
circuits.
Output from the oscillator amplifier.
Ground: 0 V reference.
Analog ground: 0 V reference. This should nominally be the
same voltage as V
and error.
PLL analog ground: 0 V reference. This should nominally be
the same voltage as V
noise and error.
1.8 V core power supply: This is the power supply voltage
for internal circuitry.
SS
, but should be isolated to minimize noise
SS
, but should be isolated to minimize
LPC2292/2294
© NXP B.V. 2011. All rights reserved.
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