LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 55

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1857_53
Objective data sheet
Table 3.
Symbol
Debug pins
DBGEN
TCK/SWDCLK
TRST
TMS/SWDIO
TDO/SWO
TDI
USB0 pins
USB0_DP
USB0_DM
USB0_VBUS
USB0_ID
USB0_RREF
USB1 pins
USB1_DP
USB1_DM
I
I2C0_SCL
I2C0_SDA
Reset and wake-up pins
RESET
WAKEUP0
WAKEUP1
WAKEUP2
WAKEUP3
ADC pins
ADC0_0/
ADC1_0/DAC
2
C-bus pins
Pin description
L4
J5
M4
K6
K5
J4
F2
G2
F1
H2
H1
F12
G12
L15
L16
D9
A9
A10
C9
D8
E3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
…continued
32
187
41
38
42
44
46
35
26
28
29
30
129
130
132
133
185
-
-
-
8
[3]
[3]
[3]
[3]
[3]
[3]
[7]
[7]
[7]
[8]
[9]
[9]
[10]
[10]
[11]
[11]
[12]
[12]
[12]
[12]
[12]
[9]
I
I; F
I; PU I
I; PU I
O
I; PU I
-
-
-
-
-
-
-
I; F
I; F
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
All information provided in this document is subject to legal disclaimers.
I
I
O
I/O USB0 bidirectional D+ line.
I/O USB0 bidirectional D line.
I/O VBUS pin (power on USB cable). This pin includes an internal pull-down
I
I/O USB1 bidirectional D+ line.
I/O USB1 bidirectional D line.
I/O I
I/O I
I
I
I
I
I
I
Rev. 1 — 14 December 2011
Test Mode Select for JTAG interface (default) or SW debug data
External wake-up input; can raise an interrupt and can cause wake-up
External wake-up input; can raise an interrupt and can cause wake-up
External wake-up input; can raise an interrupt and can cause wake-up
External wake-up input; can raise an interrupt and can cause wake-up
ADC input channel 0. Shared between 10-bit ADC0/1 and DAC.
Description
JTAG interface control signal. Also used for boundary scan.
Test Clock for JTAG interface (default) or Serial Wire (SW) clock.
Test Reset for JTAG interface.
input/output.
Test Data Out for JTAG interface (default) or SW trace output.
Test Data In for JTAG interface.
resistor of 70 k (typical)  30 k.
Indicates to the transceiver whether connected as an A-device
(USB0_ID LOW) or B-device (USB0_ID HIGH). For use with OTG, this
pin has an internal pull-up resistor.
12.0 k (accuracy 1 %) on-board resistor to ground for current
reference.
External reset input: A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0.
from any of the low power modes. Input 0 of the event monitor
from any of the low power modes. Input 1 of the event monitor.
from any of the low power modes. Input 2 of the event monitor.
from any of the low power modes.
2
2
C clock input/output. Open-drain output (for I
C data input/output. Open-drain output (for I
32-bit ARM Cortex-M3 microcontroller
LPC1857/53
2
2
C-bus compliance).
C-bus compliance).
© NXP B.V. 2011. All rights reserved.
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